ASML and IMEC prepare EUV post-immersion
The programme will include investigation into optical path stability and monitoring; lithography reticle handling (including cleaning) and defect printability; assessment of line edge roughness (LER) and its relation to shot noise; resist assessment and process optimisation; 32nm node critical layer patterning; and printable defects of masks.
The programme details will be defined in collaboration with IMEC's core partners such as Infineon Technologies, Intel, Matsushita, Philips, Samsung and Texas Instruments, in the next six months.
There is a growing consensus that 193nm immersion lithography will be introduced for 65nm half-pitch in 2007, and the outlook is positive for its extension to 45nm half-pitch. However, it will be very hard to get to the 32nm half-pitch since this would require very high-NA lenses and a high-index fluid.
"This agreement enables us to provide our partners with one of the world's first full-field EUV lithography tools," says Luc Van den hove, vice-president Silicon Process and Device Technology.
IMEC invites semiconductor manufacturers, material suppliers, mask shops and peripheral lithography equipment suppliers to participate in the programme.