News Article
STMicro in 65nm CMOS landmark
Number two European chip maker STMicroelectronics claims that it has developed a 65nm CMOS design platform.
This is the first time that such a platform has been delivered, and the company is planning to start using it to produce next-generation system-on-chip (SoC) products for low-power, wireless, networking, consumer and high-speed applications.
The 65nm library platform includes multiple process options that allow individual cells to be optimised for high performance, low power or general purpose use. Each option shrinks 90nm products by half while improving speed up to 30%.
The cells support densities of more than 800,000 gates per square millimetre and a core supply of 1.0V or 1.2V, with metal pitches of 0.20-micron and from six to ten metal routing layers.
"Being the first to deliver a 65nm design platform validates our alliance strategy, in general," said Didier Chapuis, group vice president of platform development at STMicroelectronics.
"Our customers' applications will exhibit spectacular performance at affordable costs because we've overcome the challenges to delivering the 65nm design platform."
Further extensions to the initial platform, including SOI (Silicon-on-Insulator) versions and high-performance integrated passive devices, are at an advanced stage of development and will be available soon, the company said.
The company has already completed the design – or tape-out – of a complex 65nm system-on-chip to demonstrate the new technology.
This is the first time that such a platform has been delivered, and the company is planning to start using it to produce next-generation system-on-chip (SoC) products for low-power, wireless, networking, consumer and high-speed applications.
The 65nm library platform includes multiple process options that allow individual cells to be optimised for high performance, low power or general purpose use. Each option shrinks 90nm products by half while improving speed up to 30%.
The cells support densities of more than 800,000 gates per square millimetre and a core supply of 1.0V or 1.2V, with metal pitches of 0.20-micron and from six to ten metal routing layers.
"Being the first to deliver a 65nm design platform validates our alliance strategy, in general," said Didier Chapuis, group vice president of platform development at STMicroelectronics.
"Our customers' applications will exhibit spectacular performance at affordable costs because we've overcome the challenges to delivering the 65nm design platform."
Further extensions to the initial platform, including SOI (Silicon-on-Insulator) versions and high-performance integrated passive devices, are at an advanced stage of development and will be available soon, the company said.
The company has already completed the design – or tape-out – of a complex 65nm system-on-chip to demonstrate the new technology.
