The 65nm question

Pattern-limited yield could scupper the industry's attempts to use 65nm technology to keep up with Moore's Law, writes Dr Kevin Monahan, vice president of KLA-Tencor's technology, patterning solutions group.

Pattern-limited yield may not sound like a formidable problem, but don't be fooled by its relatively benign-sounding name. Indeed, it is perhaps the greatest challenge that semiconductor manufacturers will face at the 65nm node and beyond.

"What is pattern-limited yield?" you may ask. Put simply, it is semiconductor yield limited by patterning errors that arise from the interaction between increasingly complex IC designs and shrinking lithographic process windows.

It is a design-to-process yield gap that continues to widen as feature sizes scale ever downward, critical dimensions (CDs) and overlay requirements become more stringent, and high aspect ratios become even higher.

Pattern-limited yield is part of a growing trend - that yield losses in sub-90nm processing are increasingly the result of systematic (parametric) process errors.

It is well known that most yield losses in semiconductor manufacturing are caused by either random defects or systematic process errors. Prior to the 130nm technology node, random defects accounted for the vast majority of these yield losses.

At the 130nm node, random defects and systematic process errors were roughly equal contributors to yield loss in early production. Beginning at the 90nm node, however, systematic yield loss represents an increasingly dominant share of total yield loss.

Achieving high yields in early production is becoming more difficult with each new technology node due to parametric process errors. Using past trends and pinning it to recent yield data, we can predict pattern-limited and defect-limited yields out to the 32nm node (see Figure 1).

These predictions have shown that while defect-limited yields remain relatively high over the next several design nodes, pattern-limited yields are a growing concern. In ramping a new design into production, a pattern-limited yield delay of only three to six months can cost IC manufacturers tens of millions of dollars per product.

Several techniques have been proposed to address this widening design-to-yield gap. Should it become production worthy, 193nm immersion lithography (i193) is expected to provide a substantial depth-of-focus (DOF) benefit in the near-term.

Since most failures in CD control are the result of underlying root-cause errors that change the effective dose and focus during lithographic exposure, the ability of i193 to widen lithography process windows would have the effect of improving CD control.

Unfortunately, beyond the 90nm node, the DOF advantage that i193 provides erodes rapidly - underscoring the need for a new innovation in focus-exposure control to extend lithography to the sub-90nm realm.

Advanced process control (APC) systems are also being examined as a possible solution to improving pattern-limited yields because they are likely to dramatically reduce CD errors at the lot and wafer levels in high-volume 300mm production.

However, at the 65nm node, CD error will continue to arise from hidden systematic error, including intra-wafer dose and focus errors that occur during lithographic exposure, as well as corollary systematic variation in the profiles of critical high-aspect-ratio structures. Neither has been adequately addressed by APC.

Another technique for providing focus-exposure control is optical overlay metrology. Optical overlay metrology can be adapted to provide simultaneous inline monitoring of focus, exposure and overlay directly on product wafers without impacting productivity.

It can accomplish this by using dual-tone, line-end-shortening (LES) targets. Such targets must be designed to decouple focus and exposure measurements and then placed at multiple locations in scribe lines to monitor focus-exposure variation across the field and across the wafer. This methodology is already being put into practice by several IC manufacturers-with promising results.

Techniques such as cross-sectional SEM and TEM can be used to identify the source of hidden profile errors in device structures, but are time-consuming, destructive and costly.

A new technique that has emerged to monitor device profiles directly on product wafers is spectroscopic ellipsometry. Optical film thickness platforms based on spectroscopic ellipsometry technology can be adapted to provide simultaneous inline monitoring of CD, sidewall angle, depth, and film thickness.

Typical applications of spectroscopic ellipsometry profiling technology include the complex stacks and layouts associated with shallow-trench isolation (STI), multi-layer gate structures and sidewall spacers.

A new application for spectroscopic ellipsometry is contact array metrology, which is especially critical for detecting hidden systematic error due to the association of small, sloped, or footed openings with excessive contact resistance and yield loss.

As the innovation required to stay on Moore's Law steadily escalates, it is expected that starting yields will continue their downward trajectory, largely as a result of patterning limitations.

That is, unless aggressive process control strategies are deployed to tackle emerging sources of parametric yield loss, including hidden focus-exposure and profile errors.

Emerging metrology solutions, such as the use of optical overlay with specially designed targets and spectroscopic ellipsometry, could stem the tide of pattern-limited yield loss and enable the recovery of tens of millions of dollars in revenue per factory per year.

Click here to view Figure 1

Caption for Figure 1:
Rapidly shrinking process windows have created a pattern-limited yield crisis in early volume production. Future designs must take into account much tighter margins if they are to yield on silicon.

Dr Kevin Monahan