From old school to essential

Chemical Mechanical Planarisation (CMP) is older than the semiconductor industry and was retired to an obscure history in the early development of semiconductors. Instead the technology has become the second most expensive part of the manufacturing process and a key enabler for the future of the industry. David Ridsdale takes a look at the past, present and future of the technology.

Despite the appearance as an emerging technology in the early 1990s, CMP as a process has been around much longer than the semiconductor industry itself. CMP is a form of controlled tribology. A word introduced in the 1960s to describe the science and technology of two interacting surfaces in relative motion, such as friction, wear, adhesion and lubrication. Despite the 20th century definition the science of tribolgy has been practiced since the Egyptians lubricated wooden tracks to move large stone blocks or statues.

A key factor for the development of tribology and the science that is known today as CMP was the invention of the atomic force microscope (AFM) in the 1980s. Without this improvement on the scanning tunneling microscope there would be no CMP as the process is required in semiconductor manufacturing below 0.5 µm. Without AFM the industry would be unable to probe the buried interface properties at an atomic or molecular scale.

Conventional mechanical planarisation techniques do not meet the required
specifications of wafer planarity. The chemical mechanical planarisation (CMP) process
was invented to fulfill such needs. The unique difference between ‘historical CMP process and the one used in Si IC fabrication lies in the amount of materials removed. Very thin layers of materials (typically less than 0.5 µm) are removed with precise control in the CMP process of Si IC fabrication involving embedded metals and dielectric surfaces.

Maintaining precise control of film thickness is very important to device performance and requires a sophisticated approach; it has been a challenge to both engineers and scientists since its introduction. Mechanical effects are more important on hard materials such as tungsten and tantalum while chemical effects are more important on soft materials such as aluminum and copper. As device size continues to shrink, the control of slurry chemistry plays a more important role in CMP process.

The explosive growth in CMP for planarising VLSI circuits has resulted in a high demand for equipment, consumables, and process technology. CMP has become the most expensive part of semiconductor manufacturing other than lithography. With its ability to achieve global planarisation, its universality (material insensitivity), its applicability to multimaterial surfaces, and its relative cost-effectiveness, CMP is the ideal planarising medium for the interlayered dielectrics and metal films used in silicon integrated circuit fabrication.

CMP Today

CMP is one of the most powerful advancements in the production of semiconductor devices in recent history. As stated it is one of the most expensive segments of manufacturing. Most of this cost occurs in the consumables with products including polishing pads, pad conditioners, slurries, reactive liquids, fixed abrasives and carrier films. There are three major areas for CMP in microelectronics manufacturing.

Most computer chips are manufactured on silicon substrates, but silicon carbide (SiC), gallium arsenide (GaAs), germanium (Ge) and other substrates are also used for integrated circuits, especially those used for Internet and wireless communications purposes. These alternative substrates require the same critical surfaces as silicon and are produced in much the same way.

Karey Holland of Techcet Group is a global consultant on CMP consumables for semiconductors was one of the engineers who initially felt CMP would increase defects.
Instead it was found to improve defects as well as planarise topography. Holland points out that planarising the dielectric films is critical for several reasons:

1) lithography depth of focus has been decreasing with each new generation
2) subsequent metal wires running over topography are thinned due to line-of-sight deposition
3) contact holes and via holes connecting metal lines to previous levels needed to be tapered (taking up valuable chip real estate)
4) straight walled vias/contacts required CVD (e.g., W(tungsten)) or similar fill. Etch back of the overburden W was uncontrollable without previously planarised dielectrics. For sometime, people were doing etch back of overfill W, then W CMP was developed & made a large improvement in device yield.

The major areas for CMP in semiconductor manufacturing are wafer planarisation and advanced copper and low-k solutions, especially for 90nm node and below manufacturing. Integrating copper with low dielectric constant (low-k) materials is critical to the development of next-generation ultra-large-scale- integrated circuit (ULSI) technologies.

What are the major challenges for today?

As CMP is now such an important enabling process, the entire industry is keen to identify and tackle the current technical challenges. CMPs ability with copper and low k materials will determine the rate of integration of these two materials. Fragile materials do not do so well with CMP and there is a race on to find the correct recipes to allow copper integration and to stop low k dielectrics from breaking after the CMP process.

Jean-Marc Girard of Air Liquide Electronics feels that achieving surface planarity is critical for todays processes as it puts an increasing burden on lithography to maintain depth of focus. In addition Girard says there is no proven dry etch chemistry for Cu (copper) as there is for W or Al (Aluminium) , so it is the only solution to etch back excess Cu.

Konstantin Smekalin, Sr. product marketing manager at Applied Materials CMP products division descries the challenges as multi-faceted due to different technology needs. Smekalin feels no matter the need the greatest challenge is reducing cost and increasing productivity in an industry with such tight margins. Smekalin highlighted the following for specific applications.
1.For Shallow Trench Isolation (STI) CMP, it is ever-shrinking budgets for nitride erosion and trench dishing, and also reduction in defect sizes and densities.
2. For Tungsten CMP, it is a reduction in erosion budgets to support Copper wiring topography requirements.
3. For Pre Metal Dielectric (PMD)/Inter Layered Dielectric (ILD) CMP, it is tightening of uniformity and defectivity specs.
4. For Copper, they are the need for very low down forces to preserve the integrity of fragile low-k materials that are being rapidly introduced into the BEOL, and tightening of planarity and uniformity specs that call for new technology solutions.


Future of CMP

Semiconductor devices will continue to shrink and companies will continue to look for ways to reduce costs. This is an important issue for CMP at present as the rising costs will potentially create an economic issue for the whole electronics food chain. Whilst some companies seek to reduce current costs, others are seeking new and innovative methods to ensure CMP remains a vital part of the manufacturing flow.

Joan Koppenbrink, Vice President of business development and communications at Rohm and Haas Electronic Materials CMP Technologies confirms the copper and low k issue but stresses that besides the ongoing challenge of defectivity, copper interconnects and low-k dielectrics present additional challenges. Copper CMP is significantly more complex than any of the prior CMP processes and requires at least two and often three different steps. From one copper device producer to another, the integration scheme, copper metal quality and design criteria vary substantially.

Koppenbrink comments that as a result, the goals of the CMP process can be significantly different from customer to customer. Nonetheless, in all cases erosion and dishing must be tightly controlled, and as line widths shrink, less deviation can be tolerated. Low-k adds another degree of difficulty in that the low-K dielectric can range from a silicon-based material to an organic polymer, but regardless of the dielectric choice, the mechanical stability of the material is much less than traditional oxides.

The future of CMP depends on cost reduction of consumables and innovative ideas. Jean-Marc Girard of Air Liquide summed up the feelings of materials suppliers by identifying the reduction of consumables costs. These consumables include slurries, pads, post CMP clean chemistries and other equipment related consumables. Girard adds that further optimisation of process can also reduce cost by minimizing slurry waste during the process as well as slurry waste during flushes and monitoring. For slurries which are prone to degradation with time, robust techniques for maintaining slurry consistency can also lead to cost reduction. Some of this can be achieved if the end users, tool manufacturers and material suppliers work closely to share the associated developmental costs.

This working together concept was constant in all discussions and Applied Materials Smekalin highlighted future needs suggesting the focus should be on developing new technology solutions that have cost reduction factored in at the early development stage, so it becomes a driver for process integration, hardware design, and consumable choice. Independent cost reduction for individual elements will produce less effective overall results. Smekalin felt that such coordinated cost-focused development will be a major part of the overall 65 nm technology development, and expect it to further strengthen at 45 nm and below.

The next key point for CMP is when the line widths move below 65nm. Current CMP will not be as effective and unless there is a vast improvement in current process, innovation will be required. A number of tool makers have released prototype CMP tools for below 65nm htat do not rely on current technologies. Significant new technology developments in CMP recently, particularly the introduction of full-immersion vapor dry technology, closed-loop and in-situ process control solutions, and electro-chemical mechanical planarisation (Ecmp), for copper, CMP has gained a lot of potential, and will remain effective for several technology generations to come as well as enter new areas such as MEMS ensuring innovation and competition for the industry.

Getting it right: Peeling is a common problem in CMP and one of the many to be tackled by the semiconductor industry

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