Ultra thin yield enhancement

The microelectronics industry is constantly changing with new innovations introduced. Engineered substrates are been introduced to tackle issues of speed, power and leakage. Silicon-on-Insulator (SOI) has been one of the strong contenders. Dr. George Celler and Dr. Christophe Maleville of SOITEC discusses yield challenges and solutions for this emerging technology.

Silicon-on-insulator (SOI) starting wafers are making inroads into IC manufacturing, especially for chips destined for high-speed and/or low-power applications. In SOI (silicon-on-insulator)-based IC manufacturing, traditional bulk silicon wafers are replaced by "engineered" substrates, which consist of multiple layers of substrate materials. The SOI wafer is a composite substrate with an active top monocrystalline Si layer decoupled from the support wafer. It is the first example of an engineered substrate addressing mainstream MOSFET performance requirements. SOI makes a major impact on partially and fully depleted devices in terms of performance enhancement, reduction of leakage currents and power consumption, suitability for low voltage device architectures and so forth.

SOI wafer technology has reached maturity. But the demand for thinner and thinner films places new demands on the fabrication methods. At the same time SGOI and sSOI, two strained Si on insulator technologies, are moving into the pre-industrialization phase.

The ITRS roadmap outlines scaling parameters for SOI wafers. By 2006, fully depleted devices will require silicon layers as thin as 150. With silicon uniformity of ±10%, just angstroms in variation could affect device yield, so accuracy is paramount. (The insulating buried oxide layer, or BOX, is also thinning, but not as quickly.) The need for tighter thickness control was coupled with the industry's transition to 300mm.
In addition to thickness uniformity, the other major parameter in SOI wafers is defect density. With the 300mm ramp, optimised manufacturing processes yielded quality equal to or better than 200mm, with a more aggressive edge exclusion specification: 3mm vs. 5mm for 200mm.

In parallel to ultrathin SOI, the roadmap also calls for strained silicon on insulator. By introducing biaxial tensile strain into the silicon lattice, electron mobility is substantially increased. There are several approaches to creating strained silicon (see Figure 1). In the first generation, which is targeted at partially depleted devices, the strained layer is maintained by a sub-layer template of silicon germanium. This is referred to as SGOI. In the next generation, slated for the following year, the strained silicon will be bonded directly to the insulating layer, eliminating the template layer from the final product. This is referred to by various acronyms, including sSOI and SSDOI. It is targeted for fully depleted device applications, with the strained silicon layer thickness initially running around or under 200.

SOI is also of interest to those in the MEMS (micro-electro-mechanical systems) and microphotonics domains. In SOI wafers for MEMS, the top monocrystalline silicon layer is typically quite thick (between 1 and 100µm). Monocrystalline silicon offers many advantages over traditional polycrystalline silicon, and enables the creation of more complex structures. In photonics applications, SOI enables the creation of small optical waveguides with much sharper bends than would be possible with traditional glass waveguides.

Yield Challenges and Strategies

Users of SOI wafers depend on the supplier to deliver high-quality wafers at reasonable prices. As is also the case for bulk and epi wafers, SOI wafers must meet very stringent flatness and defectivity standards. With the move to 90nm geometries, all wafer suppliers must also tackle the issues of thickness uniformity and nanotopography. What makes SOI wafers different when considering metrology techniques are the very thin top silicon films and the multiple Si/SiO2 interfaces. The challenges increase with each new scaling generation.

Site flatness and Surface NanoTopography (SNT) are two key parameters regarding device processing on a wafer. Site flatness impacts the focus budget of wafers in lithography, while SNT impacts CMP steps such as STI planarisation. SOI wafers are used in advanced device manufacturing, typically involving design rules of 130nm or below, requiring tight specifications both for lithography and process behaviour. SNT is also driven by SOI wafer manufacturing due to its impact on bonding properties. Edge roll-off is another critical parameter for wafer bonding, as it drives wafer-bonding quality in the near edge area (the last 3mm) then defines the non-SOI area on an SOI wafer.

To characterize the starting Si wafers and the SOI structures throughout the fabrication process, we require a differential interferometer. This enables us to look at both the front and back surfaces of the wafer, and to measure wafer shape, edge rolloff, thickness, flatness and nanotopology in a single scan. It also keeps roughness and reflectivity-induced artifacts to a minimum, thanks to oblique-angle illumination.

A differential interferometer eliminates the challenges that were once associated with measuring flatness on SOI wafers. Figure 2 shows a typical SFQR map on a 700/1450 wafer, using a 33x33 mm site size. When comparing the geometric properties of the final SOI wafer with the initial handle wafer used for this SOI wafer, it is clear that the final SOI flatness properties mimic the geometric properties of the base wafer.

In the most recent ITRS roadmap, both threshold and defect density are aggressively reduced as device design rules shrink. These defectivity requirements are set in order to protect device manufacturing yields, which means catching any potential killer defect at the incoming material stage. During the last generation, the starting substrate has significantly evolved. The active layer for transistor fabrication has changed from CZ silicon to epitaxied silicon and to an SOI layer. Each of these substrates has shown different killer defects as illustrated in Figure 3. Cop's has been demonstrated on CZ wafers as impacting the gate oxide's reliability. With epi substrates, crystalline-type defects can be generated during the epi layer growth, ending in large epi mounds or spikes exhibiting a very high killer ratio for devices. For SOI a typical defect type is the void. Voids are bonded defects, mainly induced by particles trapped at the bonding interface when contacting wafers. This is why tight particle control is required in all the processing steps performed on seed and handle wafers before bonding.


With the move to the ultrathin film generation, particle contamination is kept at a very low level so that SOI product defectivity is not impacted in film thickness down to 175 (Figure 4). SOI wafers defectivity is monitored using the same tool technology as bare silicon or epi substrates. Nevertheless, the SOI structure impacts the optical response from the SOI wafer (Figure 5). Whereas in a bulk wafer transmitted light is absorbed, SOI buried interfaces are able to reflect part of the transmitted light at the interface. Then, incoming and reflected beams interfere with each other, changing the apparent reflectivity of the SOI wafer and impacting surface defect scattering.

Figure 6 shows how scattering is modified depending on silicon and BOX thicknesses. Depending on destructive or constructive interference, scattering is decreased or increased and defects are undersized or oversized. Then, the wafer itself drives sensitivity rather than the tool settings. Using all available features on the metrology tool, combined with an implementation of calibration curves, SOI wafer inspection can be improved and accurate defect monitoring can be achieved. Going forward to the next design generations, more stringent requirements are described by industry roadmaps with, for example, 90 nm threshold inspection for the 65nm node. Early results show detection at the 60nm threshold, satisfying industry needs down to 45nm. It is important to note that ultrathin films (<200) offer enhanced scattering, allowing easier inspectability.


Strained silicon metrology

Strained silicon introduces new metrology challenges. The key parameters and the methods for measuring them are detailed in the "Emerging Materials" document of the 2003 ITRS as seen in table two. Some early strained silicon discussions suggested that thermal processing would relax the strain. This has been proven false for SGOI, unless the film is beyond critical thickness (as defined by Matthews-Blakeslee criterion) and is in a metastable state. The silicon thickness limitations for sSOI are more complex, and still the subject of continuing research.

The chief challenge in SGOI is ensuring that the lattice mismatch is confined to the graded buffer layer, so that uniformity in the relaxed template layer is maintained. The ITRS document makes recommendations for evaluating the critical parameters, but acknowledges that some of the techniques will be replaced for high-volume production.

Table 2 shows the key parameters for strained Si wafers and the current metrology tools for measuring them. Numerous development projects are underway to ensure that the requisite metrology tools are in place to meet the roadmap requirements. Threading dislocations and pileup densities comprise the primary potential defects. Short-range and long-range surface roughness are also issues. Short-scale roughness could impact transistor performance; long-scale roughness could impact lithography. Both are factors in metrology based on light-scattering (as discussed earlier).

To meet the ITRS targets, the industry's suppliers of equipment, materials and expertise are working on solutions for technology nodes that are still two or three generations away. Likewise, user's of today's SOI tools benefit from the accumulated expertise of the suppliers. So, as SOI enters the mainstream for leading-edge IC manufacturing, the high-volume, production-worthy metrology and inspection equipment are ready.







Dr. George Celler is Chief Scientist at SOITEC/USA. Previously, he spent 25 years at Bell Laboratories in Murray Hill, New Jersey, where he was a Distinguished Member of Technical Staff and Technical Manager. He received his M.Sc. degree from the University of Warsaw and a Ph.D. in solid state physics from Purdue University. In addition to his long-term interest in silicon-on-insulator structures and their applications, he also investigated laser annealing and rapid thermal processing of semiconductors, diffusion phenomena in Si and silicon dioxide, and x-ray lithography. He published over 170 articles, edited seven books, and was issued 15 US patents. He is a fellow of the American Physical Society and of The Electrochemical Society, a member of IEEE and the Materials Research Society. He has received the 1994 Electronics Division Award of The Electrochemical Society, and two Bell Labs President's Gold Awards.


Christophe Maleville, PhD is a process engineering manager at Soitec (Bernin, France. Since 1993, he as been involved with the development of the Smart Cut process in collaboration with the Commissariat ˆ l"Energie Atomique/Laboratoire d'Electronique (CEA/LETI) and has worked on its application to the manufacturing of SOI wafers. Currently he participates in new SOI process development and in transferring SOI technology to production. He has authored or co-authored more than 30 papers dealing with SOI manufacturing and metrology and holds approximately 15 patents in that area. He received his PhD in microelectronics from the Institute Polytechnique de Grenoble.