News Article
CSM releases manuals for new 65nm process
US foundry Chartered Semiconductor Manufacturing has released design manuals and SPICE (simulation programme with integrated circuit emphasis) models for the 65nm process platform it is jointly developing with chip makers Infineon, IBM and Samsung.
US foundry Chartered Semiconductor Manufacturing has released design manuals and SPICE (simulation programme with integrated circuit emphasis) models for the 65nm process platform it is jointly developing with chip makers Infineon, IBM and Samsung. The publication of the manuals and models is a key step forward in moving towards 65nm production at the company’s fabs.
The manuals and models will provide design engineers with the information they need to design complex system-on-chip products to be manufactured using the 65nm process.
Chartered has also announced that it is planning to offer 65nm multi-project wafers at its 300mm Fab 7 in the fourth quarter of 2005. Pilot production at 300mm on 65nm base and low-power processes is scheduled to kick off in early 2006.
The 65nm process the company is developing will offer a triple-gate oxide option, up to nine layers of copper interconnect plus a redistribution layer, and low-k inter-metal dielectrics. Compared with 90nm process, it will provide a 28% linear shrink, a 50% reduction in chip area and 200% increase in gate densities.
Chartered senior vice president of technology Dr Shi-Chung Sun said that the new 65nm process would offer major performance benefits. "Our initial 65nm devices have demonstrated an excellent balance between performance and power consumption."
The manuals and models will provide design engineers with the information they need to design complex system-on-chip products to be manufactured using the 65nm process.
Chartered has also announced that it is planning to offer 65nm multi-project wafers at its 300mm Fab 7 in the fourth quarter of 2005. Pilot production at 300mm on 65nm base and low-power processes is scheduled to kick off in early 2006.
The 65nm process the company is developing will offer a triple-gate oxide option, up to nine layers of copper interconnect plus a redistribution layer, and low-k inter-metal dielectrics. Compared with 90nm process, it will provide a 28% linear shrink, a 50% reduction in chip area and 200% increase in gate densities.
Chartered senior vice president of technology Dr Shi-Chung Sun said that the new 65nm process would offer major performance benefits. "Our initial 65nm devices have demonstrated an excellent balance between performance and power consumption."