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An ingenious new CMOS-compatible process promises to significantly improve the performance of power devices. F Udrea, T Trajkovic and GAJ Amaratunga of Cambridge Semiconductor report.

Here, we report a novel power device concept based on the use of high voltage regions suspended on thin semiconductor/dielectric membranes. The membrane power devices are manufactured in a fully-CMOS compatible silicon-on-insulator (SOI) process followed by a bulk etching step and subsequent back-passivation. The concept is applicable to a class of high voltage devices such as LDMOSFETs, diodes, LIGBTs and superjunctions.

This technology can deliver more than three times higher current density (30 A/cm2) and two to five times the switching speed (500 kHz for 650V rated devices) of state-of-the-art power IC technologies such as junction-isolation or standard SOI.

Junction-isolation devices are based on using a lowly doped p-type semiconductor substrate as part of a vertical p-n junction to facilitate a more rapid advance of the depletion region in the n-drift region of the power device. This is known as the RESURF concept. However, this technology has limited performance in terms of on-state resistance, current density and switching speed.

To reduce the on-state losses and increase the power density, lateral insulated gate bipolar transistors (LIGBT) could be employed. LIGBTs however have been unsuccessful in this technology due to injection of plasma deep into the silicon substrate. This plasma not only limits the recombination speed during the turn-off (with switching times in excess of 1s) but can be parasitically collected by adjacent CMOS blocks resulting in malfunction of the Power IC.

SOI resolves some of these issues but since the semiconductor substrate acts as a back-side field plate, the entire voltage during blocking mode must be supported across the buried oxide. This imposes a fundamental thickness requirement for the buried oxide in an HVIC. Additionally, there are limitations due to the formation of an inversion layer at the top of the buried oxide. For LIGBTs made in thin SOI layers this leads to a very early punch-though breakdown.

The use of variable lateral doping in conjunction with SOI has led to development of high voltage MOSFETs but the process is based on non-standard buried oxide layers and the use of unipolar conduction still limits the current capability, especially at high temperatures.

Other devices such as super-junctions or 3D-Resurf in SOI or SOD (silicon-on-dielectric) have been proposed to overcome these problems, but they have yet to be demonstrated in a fully-CMOS compatible high voltage process.

Membrane Power Device Concept

Here we report the use of a MEMS step (bulk micromachining), post CMOS, which allows thin membranes to be formed selectively under the drift layer of a power device.

It works by selectively removing the substrate under the buried oxide in the drift region. This leaves a thin silicon-oxide membrane that is used for supporting the high voltage. The buried oxide is used as an effective etch-stop during deep RIE ensuring a high uniformity and yield.

Figure 1 shows the cross-section of a half cell of a LIGBT on a membrane. The LIGBT is ideal for use in conjunction with the membrane technology due to its higher current capability and its increased breakdown tolerance to variations in doping.

Figure 2 shows a photograph of a multi-finger LIGBT with interdigitated cathode and anode terminals. The anode (high voltage terminal) sits on multiple finger membranes while the cathode (low voltage terminal) and the gate sit on the spaces between the membranes. In this arrangement, the thermal flow caused by self-heating can be directed away from the membrane area through the spaces between the membranes down to the substrate, to which the package heat sink is attached.

The removal of the entire silicon substrate under part of the drift region increases significantly the avalanche breakdown and suppresses the punch-through effect characteristic of thin drift layers. Figs 3 & 4 The removal of the substrate allows a near-ideal surface potential distribution in the drift region while the potential lines are released deep in the trench below the membrane (Figures 3 and 4). This is confirmed by numerical simulations and experimental data before and after the back-etch (Figures 5 and 6).

For 1µm buried oxide a spectacular 20 times increase in breakdown is obtained after the back-etch, proving the exceptional ability of the membrane to support high voltages.

A carefully engineered back-side etch does not compromise the on-state current capability of the device (Figure 7). The output characteristics of an etched and a non-etched device are virtually identical. A slight drop in current at high powers, due to the self-heating effect and a slight degradation in the channel mobility, is more pronounced in the etched device. Nevertheless, the effect of heating is considerably less damaging in an LIGBT compared to a power MOSFET. This is because the decrease in the channel mobility at high temperatures is compensated by the more active bipolar component of the device and reduced anode junction voltage drop.

The use of ultra-thin silicon layers in LIGBTs results in fast advancement of the depletion region and fast surface-type recombination, leading to record turn-off times of sub 50ns (Fig 8). To our knowledge this is the fastest IGBT reported to date. This shows that the LIGBT in the membrane technology can be faster than a classical LDMOSFET, while delivering significantly higher output current. Moreover, the absence of the substrate under the high voltage terminal yields ideal device isolation and allows fast dV/dt without coupling any significant dynamic leakage current to adjacent devices. Therefore, the technology can be applied to over 500 KHz HV switching with the prospect of increase to 1 MHz.


Back-passivation

The back-surface of the membrane is protected by the buried oxide but this may not be enough to keep the moisture out and ensure high reliability of the membrane. To passivate the back-surface, a thin PECV nitride layer was put down at low temperature following the back-etch. The results indicate that there is no damage in the breakdown or output characteristics of the device.


Power IC - full development

We developed several membrane Power IC prototypes (Figure 9) using dedicated mix-signal control/drive circuitry to optimise the efficiency of the power switch. These novel power ICs target a range of switch mode power supply (SMPS) applications ranging from a few Watts to 10-70W. Due to high speed and high current ability, fully packaged membrane Power ICs have been demonstrated to operate at frequencies in excess of 500 KHz.

When applied to SMPS architectures such as fly-back, high frequency and efficiency operation enables a hitherto unachievable reduction in the size and cost of the passives (transformer, output capacitor) resulting in higher system power density and increased efficiency.

Conclusions

This paper presents its full use in a fully integrated thin layer LIGBT.

The LIGBT in membrane technology is capable of delivering high current densities with high efficiency and fast switching. Furthermore the technology has been demonstrated in a full power IC for SMPS at frequencies in excess of 500kHz

Fig 1. CamSemi membrane power device. An LIGBT is shown in this picture, but other devices such as MOSFETs and superjunctions have been proposed in (1) and demonstrated.

Fig 2. Photograph of a fabricated 650V LIGBT on membranes.

Fig 3. Fabricated test power IC for 30W SMPS.