Lithography has been at the heart of the chip making process for more than three decades. But with the relentless demand for ever smaller feature size, has it reached its technological limit. David Ridsdale report.

The tremendous growth in the semiconductor industry has been achieved by reducing integrated circuits' cost per function by around 30% a year. The semiconductor industry has maintained this progress by improving equipment performance and throughput, enhancing manufacturing yield efficiency and increasing wafer size. The most significant contributor in keeping up with Moore's Law has been reducing integrated circuit feature sizes through advances in lithography.

Although the present form of microlithography is only three decades old, lithography itself has a long history. Alois Senefelder, a German playwright, invented lithography in 1798. For many years, lithography was a very small segment of the printing industry, used mainly by artists to produce prints. However, during the late 1800s and throughout the 20th century, great advancements in technology made lithography the most popular form of printing. Lithography found a great partner in photography when Joseph Niepce, a French scientist, produced the world's first photograph in 1826 and photolithography was born.

Modern day non-contact optical lithography was started by Perkin-Elmer in 1973 with the introduction of the Micralign 1X projection aligner. The device achieved a resolution of 4µm using an optical numerical aperture of 0.167 and operating at a wavelength of 320-440nm. During the following decade, many people estimated that optical lithography would be limited to feature sizes no smaller than one micron.

As optical lithography approached 1 micron feature size in the 1980s, it was thought that nonoptical approaches such as x-ray and direct write would be required to go below 1 micron for 1Mb DRAM generation.

But improved lens quality, higher numerical aperture lenses, off axis illumination and better processing allowed optical approaches to go below 1 micron, eliminating the need for alternative techniques.

Improvements in process and exposure tools carried the industry to the 350nm generation of 64Mb DRAM with I-line exposure wavelength of 365nm. With the delay of initial deep ultra-violet (DUV) exposure systems of 248nm wavelength, Moore's law was challenged to print the 256Mb DRAM generation.

The advent of more extreme illumination techniques, reticle enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift masks (PSM) allowed Moore's law to be met as the subwavelength imaging era began with 365nm wavelength exposures printing 250nm features. One downside of subwavelength imaging was that mask dimensional errors were no longer reduced by the reduction ratio of the exposure tools. This abruptly tightened mask dimensional specs.

With the introduction of 248nm exposures with RET, OPC, PSM, off-axis illumination and process advances, the industry supported Moore's law to 130nm feature sizes. As 193 wavelength systems became available and the 157nm and EUV systems became delayed, anxiety again ran high on how to support Moore's law, with discussions of novel electron exposure approaches as well as direct write in both electron and optical versions to meet 90nm and below feature sizes.

The ITRS roadmaps had laid out the plan to move to 157nm lithography for 130nm and beyond but once again cost of ownership of new technology and the ingenious response from engineers has meant that current technology is being extended beyond what anyone had previous imagined. With an idea borrowed from microscopy of liquid immersion applied to so called hyper numerical aperture (>1.0) systems, extensions of optical techniques to 45nm and below feature sizes are going into the fabs. Development of 157nm exposure systems is currently postponed, as the industry increasingly believes that extreme ultraviolet (EUV) will meet 33nm and below feature sizes.

Beyond 65nm, there arise a number of issues that involve more than the lithography equipment itself. At such minute parameters, the impact is felt in optics, chemicals, metrology, laser source, cost of ownership. While the general view is that the semiconductor industry will once again rise to the challenge and maintain Moore's Law, there is a change in how companies approach the new challenges. One change has been the unprecedented level of cooperation between companies and organisations. Although economically driven, these partnerships should see the adoption of standards and technology that will provide suppliers with more definitive guidelines of the industry needs and thus avoiding research wastage as seen with X-ray lithography.

In fact nobody I spoke with thought X-ray would ever be used but that was once said about EUV and it is now the front-runner for 35nm. Any decision will of course be based on the economic realities of changing technologies and unless X-ray becomes a great deal faster and cheaper, it is unlikely to be used in the semiconductor industry. As long as the chip manufacturers can push more out of the current infrastructure they will be reticent to move to anything new.

What are the challenges?
Bob Naber, director of technical marketing at SIGMA-C, believes the major challenges facing lithography will be materials, device performance, heat and economics rather than the lithographic process itself.

Phil Dembowski, global market manager for semiconductor fabrication materials at Dow Corning, says there are no particular show-stoppers for 193nm immersion lithography, but there are a few challenges that still must be overcome, including the issue of defects that can occur from using an immersion fluid. Bubble formation in the fluid and contamination of the fluid from the wafer's surface may have a significant impact on yields.

Dembowski also notes the economic challenge, as to develop future lithography applications, equipment and materials, suppliers will have to invest billions of dollars in research and development many years in advance of when the technology will be used. There is significant risk that future returns will not offset the total cost of the research and development investment. It is becoming increasingly difficult for companies to justify future technology development as the costs and risks of research and development continue to escalate with each technology node.

Casper Juffermans, head of the CMOS Integration Group at Philips Research, believes the challenges will be both technical and economic. The economic challenges are simply the cost-of-ownership of scanners and the ever-expanding mask costs. Juffermans' technical challenges are more detailed and he feels that in the short term, a potential problem for 193nm immersion lithography is bubbles in the liquid between the lens and the wafer. These bubbles can print as defects on the wafer. Practical engineering solutions for keeping the liquid free of bubbles while moving the wafer at high speed need to be proven.

For further scaling with 193nm immersion lithography, Juffermans believes an improvement will have to be made in the optical performance of the scanners. The numerical aperture of the optical system also needs to be increased further - a complex task. As resolution is further improved the polarisation of the light will become an additional parameter that needs to be controlled.

Juffermans also reckons that the most likely next-generation technology after 193nm immersion lithography will be EUV lithography. However, the cost-of-ownership and resolution performance of this new technology needs to be assessed in a user environment.

A future light
The history of semiconductor manufacturing has proven you would not want to put a bet on what will be the next lithography technology. In Europe, IMEC's sub-45nm research for lithography currently includes 193nm immersion lithography and EUV and although they the likely candidates at this time there are still other options open to the manufacturing community. The key for any supplier is to demonstrate that any contribution improves the cost of ownership as well as the technology. The chip manufacturers are looking for ways to gain more from the current lithographic infrastructure or be able to change over in a manner that enables a return of investment. With such huge costs required in R&D, there is no other option.