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New Design Approach Cuts Power Use By 40%

The Silicon Design Chain - a joint venture between equipment maker Applied Materials, foundry TSMC, chip designer ARM and electronic design automation firm Cadence - has cut the power consumption of a 90nm test chip by 40% using pioneering design methods.
The Silicon Design Chain - a joint venture between equipment maker Applied Materials, foundry TSMC, chip designer ARM and electronic design automation firm Cadence - has cut the power consumption of a 90nm test chip by 40% using pioneering design methods.

The companies say that the new design techniques will both "dramatically" increase the adoption rate for 90nm technology and pave the way for the creation of more energy efficient chips for use in portable devices such as mobile phones and laptops.

Minimising power consumption has become an increasingly important goal for chip makers in recent years. As circuits have become ever more complex, their demand for power has rocketed.

This causes two problems. Firstly, power gobbling chips quickly run down the batteries in mobile devices. Secondly, the more power a chip needs, the more heat it generates. Even older chips have to be fitted with sophisticated and expensive packaging to dissipate the heat they produce. In modern chips, it is not uncommon for the packaging needed to deal with the heat to cost more than the actual silicon die itself.

Such problems have put off some chip makers from moving to the 90nm node, where power consumption and excess heat are even greater challenges than at 130nm. One problem at the 90nm node is that transistors are so tiny that they conduct electricity even when switched off, wasting power.

But by cutting energy consumption by 40%, the Silicon Design Chain has effectively produced a 90nm IC that runs on the same power as a 130nm chip.

The secret to the power savings is software from Cadence that automatically designs the chip layout to use the minimal power. For example, it chooses which parts of the chip can run at lower voltages (what is known as voltage scaling), which can have clock signalling turned off (clock gating) and which can be made using special transistors that reduce current leakage.

"Power is one of the major issues facing our industry as we move towards the 90nm node," said Applied COO Mike Smayling. "We are excited by the work done in developing this important low-power design solution."

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