Straining at the leash
IBM has developed a new strained germanium technology that can increase the speed of transistors threefold without the hassle of having to scale them down. Huiling Shang of IBM Research reports.
The industry is quickly realising that it cant continue to improve performance in the same way it has been done over the past few decades. Instead, companies will need to discover new and innovative materials and techniques to continue down the path of Moores Law...and beyond.
Facing this problem, researchers are looking for innovative ways of improving system performance by using new processes and materials. IBM researchers recently demonstrated a technique that triples the performance of a standard transistor used in semiconductors by a process that is compatible with conventional CMOS technology. This is a major step towards achieving continued performance enhancement of chips and the electronic systems that use them.
The technique involves the creation of a layer of the element germanium (Ge) in the channel, a critical portion of the transistor through which electrical current flows. Germanium has long been known to have better conductivity than silicon, and the strain in the germanium layer created by IBMs process leads to even further performance gains.
In December, IBM presented the findings from this research project at the International Electron Devices Meeting (IEDM) in San Francisco.
The semiconductor industry has recently embraced the concept of enhancing circuit performance by boosting the transistors current transport properties. One such example is the introduction of strained silicon, which is in production by several companies today.
Strained germanium (s-Ge) has been shown to have significantly better transport properties than silicon or strained silicon. However, until now there has not been a path to enable the combination of strained germanium with conventional circuit fabrication techniques. In the recent research project, IBM has demonstrated methods that can selectively place the strained germanium on the selected areas of a chip using a CMOS-compatible process.
The introduction of a new material like germanium in the critical areas of the integrated circuits provides an alternative means of improving chip performance from the traditional method of simply shrinking circuitry. This is becoming increasingly important as further miniaturisation becomes more difficult and yields diminishing returns. IBM believes this new technique could help ensure continued performance improvements in chips with circuit sizes of 32nm and smaller.
System performance depends on chip performance, and that will increasingly depend on new materials and design techniques rather than simple scaling. The introduction of new materials in semiconductors can have profound effects, often creating new problems in other areas or demanding radically different manufacturing processes.
What is unique about IBMs results is that the selective introduction of strained germanium only in the critical areas of the integrated circuit provides a transistor with three times the performance without affecting other devices or circuits on the same chip.
This dramatically reduces the risk of introducing a new material.
Within the transistor itself, IBMs selective strained-germanium technique actually introduces other fringe benefits. For example, the integrated circuit industry is looking for solutions to replace conventional SiO2 gate oxide using high-k insulators.
However, introducing a new high-k insulator material to the existing silicon technology is found to be especially challenging; the electrical properties of the strained germanium actually provides an easier path for the introduction of high-k insulators.
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Figure 1. A schematic diagram of IBM’s proposed ideal CMOS structure, where PMOSFETs employ a buried s-Ge channel while NMOSFETs employ a Si or strained Si surface channel |
Author
Huiling Shang is a research staff member at IBM Research in Yorktown Heights, New York.
