Lead astray

The move towards lead-free electronic devices has thrown up a number of challenges for package designers and manufacturers. George Carson and Michael Todd of Henkel Corp take a look.

As electronic devices become increasingly integrated with their package, solders and packaging materials for microelectronics applications must develop at a similar rate to meet requirements.
Two particular areas that the components industry is focused on at present are concerns about the toxicity hazards associated with the use of lead in solders and coatings, and the increased demands on encapsulating materials performance as a result of denser and more complex circuitry.

The first of these is, of course, well-known and receives regular publicity, as EU legislation and regulations continue to impact the future use of lead in all areas of electronics not just in Europe, but worldwide. The second is perhaps not so widely talked about in the press but is no less critical in its importance to the industry.

Indeed, whereas we can be reasonably certain in the shorter term what is expected of us to comply with lead-free restrictions, the degree to which component design will stretch our ingenuity over the next few years is a challenging unknown. Here we review some of the latest materials requirements and how the industry is addressing the issues.

Lead-free meets
flip chip and low-k
The major trend in electronic products today is to make them smaller and faster without detriment to reliability and robustness, while also driving down cost. One of the key technologies that makes these aspirations possible is the flip chip device, which provides the shortest possible leads and the highest interconnect density within the smallest footprint. The combination of lead-free solders and coatings and increasing packaging density creates many challenges for the manufacturer of flip chip fabrication materials, as elevated processing temperatures and new surface treatments bring the potential for higher defect rates.

Now that lead-free processes have been introduced, we are accustomed to quality products being introduced with second-level lead-free interconnections. For the flip chip, however, these more brittle alloys, with their associated higher processing temperatures, can cause cracking of interconnects, a problem that is exacerbated with the growing popularity of low-k copper integrated circuits.

The performance advantages of low-k copper ICs are evident – copper can carry higher currents and transmit higher signal speeds at finer pitches. But although this makes for a smaller total footprint, the assembly is more fragile due to the inherently weaker low-k dielectric materials, which suffer from low interfacial adhesion strength between the dielectric and metal layers of the silicon stack, and reduced fracture strength.


Underfill optimisation
At least 50% of the stress placed on a low-k die by the packaging material comes from the curing of the material due to chemical shrinkage, not its physical properties. Earlier underfill formulations create too much stress for reliable operation, so ideally cure shrinkage, coefficient of thermal expansion (CTE) and modulus all need to be lowered. However, some of these properties are mutually exclusive – low CTE implies high modulus, for example – and so optimisation is the key. Fortunately, through the development of polymer systems that exhibit reduced chemical shrinkage during cure, plus improvements in filler systems, we now have access to material systems providing lower package stress, better flow performance and improved reliability.

Flux residues and adhesion
New surfaces used in advanced lead-free packages pose another challenge for the performance of packaging materials. For die-attach, the move to lead-free materials – usually Ni-Pd-Au – on lead frames has driven the investigation and optimisation of the adhesive qualities of different materials (we have found product developments based on bismaleimide chemistry to offer the most reliable performance in this respect).

Similarly, the interaction between the flux and the underfill is important for the long-term reliability of underfilled flip chip devices. When properly processed, no-clean or low-solids flux residues do not degrade electrical performance such as surface insulation resistance (SIR) or electrochemical migration (ECM), but thin films of flux residue, present on the solder bump, substrate or die, can significantly reduce interfacial adhesion between the underfill and the surfaces.

New package geometrics that are being developed, featuring smaller gaps, denser arrays and longer flow distances, may also pose problems for fluxes: flux residue build-up in the gap between bumps or between the die and the substrate can narrow the gap to a point where the flow of underfill is impeded or the edges flow faster, encapsulating air and creating a void.

Despite flip chip reflow taking place under nitrogen, the effect is even more profound at the elevated lead-free processing temperatures, which only serve to worsen matters by significantly changing the characteristics of these flux residues. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill may delaminate from the surface, forming a gap.

The role of underfill – effectively that of mechanically coupling the die to the substrate, and thereby constraining the stress on the solder joints – is diminished, and rapid fatigue failure of the solder joints follows. One solution to counter this is to incorporate a cleaning agent into the underfill – Hysol FC (flux-compatible) underfills for example. This method effectively removes the flux residues from the vicinity of the soldered joints where good adhesion is critical and disperses them throughout the bulk of the underfill, where they are safely encapsulated.

Towards package level
systems integration
Increasingly, customers are now expecting us to provide them with a material set solution, as many do not have in-house modelling and prototyping abilities. Typical components include tacky flux, solder paste, flip chip underfill and mould compounds, and the ability to supply these as a qualified set leads to shorter development cycles and lower costs for the customer.

There is also a demand for simplification of the fabrication processes, making application easier and taking the cost out at the same time. This is leading to an increase in the availability of pre-applied materials, as the materials industry invests in dicing tapes or perfects techniques for pre-applying films at wafer package level and mass-printing of materials, moving away from time-consuming and expensive needle dispensing.

These advances bring their own challenges, such as optimising the print squeegee motion to avoid trapping voids behind solder bumps during stencil printing, and to ensure that the wiping motion is effective in cleaning the solder bumps so that they are not left contaminated by underfill.

Current and future needs
From the above discussion, the current needs of component manufacturers can be broadly summarised as: low-shrinkage underfills, with a CTE that matches the CTE of solder bumps as closely as possible; flux-compatible underfills that reduce the risk of delamination or voiding due to contamination by flux residues; materials sets that include matched products, reducing development time and lowering costs for the customer; and pre-applied solutions that improve the speed and ease of underfill application, making the chip-attach process more transparent to the electronics assembler.

And for the future? Thats another story – but if the last five years are anything to go by, in another five years time, we can almost certainly expect to be working with processes that are not known today, and looking for innovative ways to make them as reliable and cost-effective as technology allows.

Figure 1. An advanced flip chip package offers the highest interconnect density with the smallest footprint

Figure 2. An advanced cavity BGA package requires an underfill with optimised properties to ensure reliable component performance

Figure 3: A silicon wafer coated with pre-applied underfill