Beam me up, Scottie

Once mainly used in research, electron beam lithography is playing an increasingly important role in semiconductor fabrication, write Juergen Gramss, Ulf Weidenmueller and Ines Stolberg of Leica Microsystems Lithography.

Electron beam lithography has long been accepted as a valuable technology in research and science. This is thanks to its flexibility and nearly unlimited resolution capability. The technology can achieve resolutions of sub 50nm – far finer than is currently possible with conventional optical lithography. Since its introduction more than 30 years ago, electron beam lithography has played a vital role in such challenging research areas as nano and biotechnology. It is unlikely that these fields would have advanced as quickly as they have without the help of electron beam lithography.

Electron beam lithography is also often employed to make the masks used in optical lithography – another area where the technologys high flexibility and ultra-fine resolution have shown their worth. In the past four or five years, electron beam lithography has also been put to industrial use as a direct write technology for Si based production. This technique is known as electron beam lithography direct writing (EBDW). But while EBDW is able to achieve resolutions that are simply not possible using conventional optical lithography, the technologys low throughput rate and the high complexity its exposure tools were regarded as show stoppers, preventing its use in semiconductor production.

This is beginning to change for two reasons. Firstly, as integrated circuit designs have become denser and more complex – a trend that is set to continue as the industry enters the 65nm node and beyond – the cost and time scale for delivering masks has rocketed. It can cost a staggering US$1.5 million and take as long as 100 days to produce a mask set for the 65nm node. IC suppliers have understandably started to look at alternative methods in order to minimise these costs and cut the time to production. EBDW is one of the techniques that have been examined.

European chip maker STMicroelectronics has been one of the pioneers in using the technology. The firm already has two electron beam lithography systems in operation (1). It is easy to see why such companies have been won over by EBDW. It is possible to make a prototype integrated circuit using EBDW in just ten days. Compare that with the 100 days that it can take to make a leading edge mask set for optical lithography.

The second reason why EBDW is growing in popularity is that significant progress has been made in speeding up the technologys throughput performance – formerly its Achilles heel.

One technique has been to mix and match different lithographic processes. The “slower” EBDW is used only for critical layers with very small patterns while non-critical layers are written by the faster optical lithography. We will look at other techniques that have been used to boost throughput later in the article.

Thanks to these two factors – the high cost of making masks and improvements in throughput – EBDW is being considered for an increasingly broad range of applications, from chip design testing for the next technology level to fast prototyping and specific niche applications.

It is interesting to note that when electron beam exposure systems are used at a particular technology node, they actually need to offer finer resolution than the node resolution.

For example, electron beam exposure systems for use in the 65nm node need to be able to resolve 45nm gates. Apart from dealing with a minimum feature size of 65nm dense patterns and 45nm isolated lines, the overlay accuracy also has to be verified.

It is further important for the electron beam process step to be compatible with the standard technology processes used by the semiconductor manufacturers. Such issues as substrate sizes (up to 300mm diameter), the alignment strategies, the overlay accuracy and complementing other lithography process steps must therefore be considered. Besides the need to work in harmony with the optical lithography process, it is also necessary to consider process-relevant steps such as the introduction and evaluation of appropriate high-resolution and high-sensitive chemically amplified resists (CAR).

Despite such challenges, EBDW has been shown by companies such as STMicroelectronics to be a feasible technology for fast prototyping and low-volume production under real manufacturing conditions. There are indeed already e-beam exposure tools available that meet the requirements of the 65nm technology node (2), namely full 300mm capability, overlay accuracy of <25nm, 45nm gate length, 90nm contact holes (Figure 1) and critical dimension (CD) uniformity < +/-10% CD.

Electron beam lithography can be used already at even smaller feature sizes – at the 45nm and 32nm nodes. Moreover, electron beam lithographys use is not limited simply to an alternative solution for research and development applications. It can complement other technologies. For example, it has been used to achieve resolutions of 35nm and below for template fabrications in nanoimprint lithography (3).

Another advantage of electron beam lithography is that it provides a new approach, which is equivalent to optical lithography. It can be used by semiconductor manufacturers to create their own in-house processes for a faster turnaround from design to the exposed structures on the wafer.
However, one factor that is crucial in the successful application of electron beam lithography in a production environment is throughput performance. This is especially true at smaller technology nodes where the pattern density challenges the serial exposure method of electron beam lithography.

A lot of effort is being put into overcoming this challenge using sophisticated correction methods and improved process optimisations during the exposure. The aim is to achieve a constant throughput rate in spite of a constantly growing pattern density. The projection of large complex patterns, as is the case in shaped beam tools, is vital in improving throughput performance. However, to improve throughput performance, the patterns have to be optimised before they are exposed. This has to be taken into account when designing the predefined shapes.

Another approach is the parallelisation of electron beam lithography as practised for maskless lithography (ML2). In contrast to extreme ultraviolet (EUV) lithography – which is the current favoured next generation lithography technology – the parallelisation of electron beam lithography dispenses with cost-intensive masks. In the case of maskless lithography, the patterns are transferred using an array of many freely controllable electron beams. This approach makes it possible to achieve a throughput performance that meets the requirements of the semiconductor industry.

However, the first ML2 tools will not be available before the introduction of the 45nm node, with resolution specs of 40nm and better (4).

Since the same exposure principle is used for both ML2 and EBDW, the latter (EBDW) is considered the ideal basis to prepare these technologies. STMicroelectronics has already described EBDW as the first maskless approach.

“Maskless e-beam lithography is firmly established as the method of choice for fabricating small structures in the sub-50nm range of sizes. We expect to see an increasing role in mainstream VLSI development and manufacturing in the next few years as well,” said Dr Timothy Groves, director of technology at Leica Microsystems Lithography and consulting professor of electrical engineering at Stanford University.

Figure 1. Critical levels of a 65nm node SRAM cell printed with e-beam direct write2

Figure 2. Minimally resolved final features on the template