Sent packaging
The future of packaging was the theme of a recent symposium held in Japan. European Semiconductor Magazine reviews some of the key points to emerge from the event.
During the first Annual SiP Technology Symposium held in January in Tokyo, Japan, key executives and technologists from leading semiconductor companies shared their perspectives on achieving greater electronics miniaturisation and performance through advanced electronics packaging.
The need for system co-design emerged as a consistent theme throughout the half-day event, as industry leaders called for greater collaboration at every stage of the design process. David Tuckerman, Tesseras chief technical officer, kicked off the event with a keynote address on lowering the risk of SiP implementation. Tuckerman said that in many cases SiP implementation is often less risky than system-on-chip (SOC) implementation. The use of the packages third dimension is critical to the development of novel electronic products, such as personal digital assistants (PDAs) that can take the form factor of a pen.
Henry Utsunomiya, president of Interconnection Technologies, provided an overview of market trends and applications for multiple-die packaging and echoed the key themes of the event, calling for closer cooperation between electronic product manufacturers, semiconductor manufacturers and materials suppliers to support the development of next-generation electronic products. Craig Mitchell, vice president of marketing at Tessera, presented a new design methodology referred to as SLIM, for system-level integration and miniaturisation. SLIM-designed systems eliminate unnecessary levels of interconnect and take full advantage of the packaging and interconnect technologies currently available to achieve significant size reductions while enhancing product performance.
3D design tools and advanced substrates were identified as key building blocks of SiP systems throughout the symposium. Gordon Jensen, president of CAD Design Software, introduced a 3D design tool with a manufacturing feedback system that allows complex 3D packages to be readily designed and optimised for volume manufacturing.
Kimitaka Endo, manager of the R&D division at North, discussed Norths copper-bump interconnect technology, which can be used to create high-density, multi-layer substrates. Hiroyuki Okabe, technical manager at Hitachi Cable, argued that flex-based substrates could deliver high density, thin profile, high reliability and low cost, key requirements in advanced consumer, wireless and computing electronics.
Spansions Junichi Kasai, vice president of final manufacturing R&D, reviewed the main challenges facing Spansion when integrating logic and memory devices in the footprint of a single package. He discussed a 3D virtual design system that Spansion is using to help address the design, cost and time-to-market challenges associated with mixed-device type integration. Ichiro Anjo, Elpida Memorys senior manager, production eng-ineering department, forecast that as DRAM chips move toward higher speeds, they would need to be packaged in FBGAs. With this shift in packaging, new stacking technology will also be required to meet the increasing demand of next-generation products. He went on to review a number of stacking techniques that could meet this demand.
IBMs Jonathan Hinkle, design engineer, discussed the need for advanced packaging in blade server applications to meet high-density memory requirements. One such example involves the combination of package-stacking technology in a new format memory module called a VLP (very low profile)-DIMM. This combination results in a 62% reduction in the board space required in a blade servers memory subsystem. Joseph Fjelstad, co-founder of Silicon Pipe, reviewed the topic of emerging trends in advanced IC packaging and interconnection for high-speed applications. He explored an innovative copper-based interconnect technology designed to close the 10x interconnect gap between signal speeds on ICs and PC boards.
If this event is anything to go by, the packaging side of chip production – previously the unsung companion of front-end work – is becoming an increasingly important and interesting field.
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