Texas Instruments achieves 65nm milestone
The company says that its 65nm technology – based on strained-silicon – boosts transistor performance by 40% and reduces leakage power from idle transistors by a factor of 1,000.
"Our 65nm process technology gives us the ability to pack hundreds of millions of transistors that support both analogue and digital functionality in tightly integrated system-on-a-chip solutions," said TI chief technology officer Dr Hans Stork.
"By delivering the industry's first 65nm device for the wireless market, TI is giving mobile customers access to more processing performance for the most advanced applications in a smaller, lower power chip."
The company's 65nm process includes up to 11 layers of copper interconnect integrated with a low k dielectric to reduce active power consumption.
Other features include an induced strain on the transistor channel to increase electron and hole mobility, nickel silicide to lower both gate and source/drain resistance and ultra-shallow source/drain junctions.
The company says that the 65nm process will enter fully qualified production on both 200mm and 300mm wafers in late-2005.