Finding the best solution

Extensive research has been carried out to determine the impact of different slurries on post chemical mechanical planarisation topography and electrical performance. Dr Zvezdalina Stavreva and Dr Goetz Springer of Infineon and Roger Tushingham, Jim Schlueter and Sanjay Basak of Novellus Systems present the results of this research.

As copper interconnects become more and more widely used in semiconductor device fabrication, it is increasingly important to understand the impact of copper chemical mechanical planarisation (CMP) processes on device performance.

It has been widely believed that the best copper CMP process would be the one that generated the least topography, with minimal dielectric and copper loss. The low topography ensures that multiple layers of metallisation can be stacked on top of each other without depth of focus or etch uniformity issues, while the low metal loss ensures the maximum amount of copper is left in the feature, therefore resulting in the minimum resistance for the line. This is supported by figure 1, which illustrates two possible process flows, both of which provide the same final topography, but have different metal loss values resulting in different resistance values.

There have been several papers describing the dependencies between CMP parameters, consumables and process results in terms of topography [1]. However, one of the challenges of the current integration schemes for copper-based metallisation systems is the presence of topography from previous levels, such as tungsten contact or pre-metal dielectric. The sensitivity of the copper CMP process to this already existing topography is still not well characterised.

In addition to dishing and erosion investigations, this article is focused on slurry comparison and performance with regard to existing topography. Furthermore, it deals with the correlation between the post CMP topography and electrical parameter results.

Experimental set-up
In this study, four different copper CMP slurries have been investigated. Table 1 (p53) summarises the major slurry properties and process parameters. In all cases, the Novellus Momentum platform was used as a polishing tool.

After detailed evaluation of the post copper CMP topography, the same barrier CMP process was applied to all wafers. This allowed a direct comparison of the four different copper slurries regarding electrical parameters performance. The barrier CMP process was performed on a different polishing tool and can be characterised by selectivity between Ta, copper and SiO2 of 1 to 0.65 to 0.25 respectively.

Two different types of patterned test wafers were used for topography evaluation and electrical parameter comparison. Test chip I comprises single damascene copper CMP test features embedded in silicon dioxide [4]. A summary of the test features used for this work can be found in Table 2 (p54). The size of each array is around 1x1mm2. This test chip is used to investigate post copper CMP topography and over polish sensitivity for different metal patterns. The topography measurements were done at different stages of the polishing process, ie during and after the transition from copper to barrier (referred to as end point) was detected.

Test chip II is a short loop with a tungsten (W) based contact to active (CA) level followed by a single damascene copper-based metal level. This test chip consists of a variety of serpentine features with different line widths and spaces, with and without contacts underneath. Test chip II is mainly used to compare the electrical performance of the four different copper CMP processes as a function of previous level topography. This comparison was done after the barrier CMP step was performed. Additionally, this test chip comprises dishing (80x90µm2 copper pad) and erosion (80x90µm2 array of 230nm copper lines and 230nm spaces) features.

Results and discussion
Figure 2 shows the topography results for the two different features on test chip I and all four slurries. The topography is plotted as a function of the over polish percentage. Over polish percentage is a ratio of time polished after end point is detected to the time taken to reach end point. For manufacturing reasons, it is generally desirable for slurries to be insensitive to over polish, ie to maintain the same topography regardless of how much over polish is used. For the 100µm isolated lines, the topography is caused by dishing. For the 83% density arrays, the measured topography is assumed to be the sum of dishing and erosion.

The best final topography was obtained for slurry C. As can be seen from Figure 2, both features show post copper CMP topography at end point below 5nm. For slurry B both patterns, the 100µm isolated line and the 83% density array show post copper CMP topography of about 20-25nm. Slurry A and especially slurry D show higher post copper CMP topography values for all investigated features. The topography for slurry D ranges at end point from 45nm to 50nm for the 83% density array and 100µm isolated line respectively.

The observation described above correlates very well with the over polish sensitivity observed for these four slurries (figure 2). The best over polish performance was obtained for slurry C. Also, for very high over-polish, almost no increase in the topography can be seen. The post copper CMP topography remains below 10nm. By contrast, slurry A shows within the investigated over polish range a significant increase in the topography of up to 50nm to 100nm for the 83% density array and 100µm isolated line respectively. For slurry D, the topography increases up to 70nm.

The topography results from test chip II are summarised in figure 3. These results are obtained for comparable over-polish percentages for all four slurries (around 50%). The dishing values for the 80x90µm2 pad confirm the results for the 100µm isolated pad on test chip I. Slurry C shows the lowest dishing of -10nm which corresponds to a slight protrusion of this feature. For all other slurries, significantly higher dishing values were observed. The topography of the array consisting of 230nm lines/230nm spaces is dominated by erosion. For this feature, slurry C shows the lowest erosion of less then -5nm (corresponding to a slight protrusion) followed by slurry B. In case of slurry B, almost no erosion can be seen. Slurry A and especially slurry D show higher post copper CMP erosion values, up to 5nm and around 7nm respectively. Apart from slurry C, the erosion performance correlates to the copper-to-Ta selectivity values given in Table 1.

In summary the best post copper CMP topography performance and over polish sensitivity was obtained for slurry C. Therefore using slurry C, a copper CMP process with an excellent final topography and high over-polish margin can be achieved.

After evaluation of the post copper CMP topography, the same barrier CMP process was applied for all test chip II wafers. Figure 4 shows a comparison of the metal short rate observed for all four copper slurries. This data summarises the results observed for different serpentine features with different widths and spaces. It can be seen that in the case of no W contacts underneath the copper lines, all four slurries show comparable shorts results. By contrast, slurry C shows a significant higher short rate compared to all other slurries in the case of W contacts underneath.

This observation can be explained by the very good planarisation properties of slurry C that make this process very sensitive to already existing topography from the W CA level. Figure 5 illustrates this mechanism, in which pre-existing topography can result in copper pools which can then lead to shorts. As already discussed, slurry C shows a very good over-polish performance. Therefore, no improvement of the short rate can be expected by increasing the over-polish time.

Figure 6 represents the stacked wafer map of the short rate data. The highest short rate was observed for the wafer centre. This confirms the proposed mechanism since it corresponds to a characteristic of the current tungsten CA CMP process, which exhibits higher topography at the centre of the wafer compared to the edge (for these test wafers, the tungsten CA CMP process was performed on an early generation rotational CMP system).

In order to analyse the details of this observation, the influence of the contact density at the W level on the short rate was investigated. As it can be seen from figure 7, the increased short rate for slurry C is caused mainly by features with small contact space – below 0.4µm. Furthermore, the short rate increases dramatically with decreasing contact space, up to a factor of 25. For contact spaces above 0.4µm, no influence of the contact space on the short rate can be seen. In this case, the short rate is comparable to the short rate of features without CA underneath (see also figure 4). These results can be explained by increasing post W CA CMP erosion with decreasing contact space. For all other slurries, the short rate shows no significant dependency on the contact space at W level. This observation confirms the lower sensitivity of slurry A, B, and D to existing topography from the previous level.

Summary
A systematic investigation of four copper slurries regarding post copper CMP topography was presented. Throughout this work, the Novellus Momentum CMP platform demonstrated the flexibility to adapt to the different polishing mechanisms of the slurries.

In summary, the best copper slurry in terms of post copper CMP topography and over polish sensitivity fulfils the basic conditions for a robust and high performing process.
When characterising a CMP process, one has to consider the influences of various integration related issues, such as pre-existing topography from underlying layers.

Applying the same barrier CMP process, the four copper slurries were compared in terms of electrical performance and sensitivity to existing topography from the W CA level.
As the results indicate, generating the theoretical best copper CMP unit process does not always result in the best electrical performance for a device. It was found that the slurry with the best planarisation properties makes the copper process highly sensitive to already existing topography. There are several ways in which the impact of these issues can be reduced. These include, but are not limited to, increasing the amount of dielectric polish to try and eliminate the copper “pools” during the barrier step.

However, this is not well controlled and can have a negative impact on overall device performance due to reduced copper line height, and increased resistance of the metallisation. The most attractive solution is a reduction in the topography resulting from tungsten CA CMP, and this will be the focus of future work.

Table1. Summary of key slurry properties and process parameters for different Cu slurries.

Table 2. Summary of test chip I features.