Process development
AMD and Fujitsu's joint Spansion Flash memory subsidiary has presented a three-year vision and strategic road map, outlining plans to scale its MirrorBit technology to 8Gbit densities on 65nm lithography to meet the demands of the entire Flash market - from wireless handsets and embedded systems to detachable cards and USB drives. The company also plans to develop a new "ORNAND" Flash memory architecture - a nitride-based technology that brings together the best of NOR code execution and NAND data storage capabilities in a single product based on MirrorBit technology.
Dr Bertrand Cambou, president and CEO of Spansion, comments: "Our upcoming MirrorBit products are designed to transcend the NOR versus NAND debate and provide our customers with optimal solutions for both code and data storage. With innovations such as Spansion's ORNAND architecture, we can enable our customers to create highly differentiated systems or even invent entirely new product categories."
Spansion plans for its MirrorBit technology to encompass the complete range of densities, performance, cost and reliability required by the overall Flash memory market. Samples of the industry's first 90nm 1Gbit NOR device and new mass data storage products for mobile phones are due from Spansion in early 2005. Further scaling will lead to 8Gbits by 2007.
The first of Spansion's new ORNAND products is expected to become available in 2005 with burst-write speeds up to four times faster than current NAND products, and all the inherent benefits of MirrorBit NOR technology, including high reliability, fast read speeds and low cost. By 2007, Spansion plans to offer a full portfolio of ORNAND products scaling to 8Gbit densities.
As a result, Spansion expects MirrorBit technology to serve the anticipated $8.9bn per year data storage market (Web Feet Research estimate) previously served primarily by floating-gate NAND-type products. Spansion also expects to create new types of memory solutions, based on the ORNAND architecture, incorporating logic functions like high-security cryptographic processors or integrated memory controllers. MirrorBit can store two or more bits of data in a single Flash memory cell.
A working proof-of-concept "QuadBit" test chip has been produced in the company's Submicron Development Center. In addition, Spansion has a working test chip prototype based on 65nm MirrorBit technology, proving the technology's scalability to smaller process geometries.
One market that Spansion definitely plans to cover is mobile phones. The company will produce a single Flash memory platform capable of delivering combined code and data storage from 16Mbits to 5Gbits. This "RS family" single platform concept will allow handset manufacturers to incorporate advanced multimedia capabilities - such as photos, video and music - in the same handset platform that also provides simple voice and SMS text messaging services. An initial 1.8V, 512Mbit product is planned for early 2005. The 5Gbit devices are anticipated for 2007.
Spansion expects that Flash memory requirements for mainstream phones will jump from about 150Mbits per phone in 2004 to more than 500Mbits in 2007. High-end phones require even more Flash memory, from about 750Mbits today to an estimated 5Gbits and beyond in 2007.
Spansion will introduce its data storage devices in stacked multi-chip products (MCPs) to support a wide variety of mobile phone designs and minimise circuit board space requirements. Spansion expects to begin sampling multiple MCP configurations, featuring up to 1.25Gbits of Flash memory, in Q1 2005.
Analog Devices (ADI) has developed a new semiconductor manufacturing process that combines high-voltage silicon with submicron CMOS and complementary bipolar technologies. The industrial CMOS (iCMOS) process technology is designed for high-voltage applications, such as factory automation and process control. iCMOS analogue components can withstand up to 30V supplies while reducing power consumption by up to 85% and package size by 30%, says Analog. An optional drain extension allows operation at up to 50V.
Among iCMOS's chief attributes is its ability to fully isolate components from the substrate or each other. That means a single chip can mix-and-match 5V CMOS with higher voltage 16-, 24- or 30V CMOS circuitry, with multiple voltage supplies running to the same chip.
Denis Doyle, ADI fellow, Process Development, comments: "Prior to the iCMOS development, industrial designers considering an analogue CMOS product for its cost or power efficiency benefits were forced to add significant levels of signal conditioning, signal biasing, and external op amps to get the high speed and low power consumption required to interface to high-voltage industrial systems ranging from actuators to sensors. Under those conditions, manufacturing technologies capable of handling 30V were in the range of 3.0microns to 5.0microns, and adding digital functionality caused them to grow to unacceptable sizes. iCMOS makes this approach obsolete by enabling the integration of more signal chain functionality into a much smaller footprint without compromising performance."
The company has introduced 15 new iCMOS analogue components based on the new process. These include digital-analogue (DAC) and analogue-digital (ADC) converters, op amps, and high voltage switches and multiplexers.
NEC Electronics claims the industry's first pseudo-static random access memory (PSRAM) device designed in accordance with Common Specifications for Mobile RAM (COSMORAM) Rev.3, a memory interface standard developed and promoted jointly by Toshiba, Fujitsu and NEC Electronics for the mobile handset market.
"The rapid evolution of mobile handsets with advanced functions such as music playback, digital image processing, games and videoconferencing has spawned a need for memory devices that offer a combination of superior performance with low power consumption," comments Masazumi Ikebe, general manager of NEC Electronic' System Memory division.
NEC Electronics developed a new type of delay circuit to regulate the internal pulse mechanism. A 32bit high-speed input/output (I/O) interface doubles previous data transmission speeds achieved with 16bit interfaces, enabling rapid communication with the handset's central processing unit (CPU). Three driver output settings allow system developers to adjust the level of noise and the optimal configurations for their applications. In standby mode only necessary memory blocks remain operational, thereby enhancing power savings.
The company's uPD46128953 device has a 128Mbit memory capacity and achieves a stable operating frequency of 83MHz during burst mode while maintaining a low operating voltage of 1.8V. Samples of the uPD46128953 product will be available in December 2004 with mass production scheduled to begin in March 2005. Monthly production volumes are expected to reach 1mn units per month.
