Design
IPP 4 1.0 provides a means of retaining information about an IP Virtual Component (VC) all the way through the chip design process, from source code to the GDS II physical database that is used to make photomasks.
"One of the shortcomings to IP-based chip design has been the lack of a method for tracking the history of the design development of a piece of IP during chip design," says Ian Mackintosh, VSIA director and OCP-IP president. "VSIA's soft- and hard-IP tagging standards give IC developers the means of tracking important IP information, including source, version, date and IP provider."
The soft IP tagging standard takes identification information from the IP source file and provides a process for passing this information through each chip-level design step. This information can include identification, vendor ID, and, most importantly version information, allowing a chip designer to explicitly identify the version of a piece of soft IP even after it has been absorbed in the overall "sea of gates" of the chip. Foundries can use the standard to provide additional services to support a quality check prior to IC manufacturing.
