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Process development

ASM International is claiming a breakthrough pore-sealing process for next generation integration of porous low-k insulator materials in copper interconnect on semiconductor chips.

ASM International is claiming a breakthrough pore-sealing process for next generation integration of porous low-k insulator materials in copper interconnect on semiconductor chips.

The plasma benzocyclobutene (BCB) polymerisation technology has been developed jointly with a major semiconductor device manufacturer to seal pores in frothy low-k materials. Open pores allow metal to get into the low-k material, reducing the effectiveness of the insulation and its dielectric properties. Dow Chemical markets BCB as "Cyclotene" for "back-end" IC packaging applications. The new front-end process is available on ASM's Eagle plasma-enhanced chemical vapour deposition (PECVD) system.

The ASM technique has already been proven as a "pore sealing process" and is targeted for implementation at 65nm. ASM claims that the process will work on most industry-developed low-k PECVD dielectrics and inorganic spin-on dielectrics in addition to the company's own Aurora ultra low-k (ULK) material.

"Due to the particular properties of the BCB molecule, the dielectric constant of the ULK material remains low", comments Ivo Raaijmakers, chief technology officer and director of R&D of ASM's front-end operations. Tominori Yoshida, business unit manager of ASM's PECVD product lines adds: "Customer demonstrations on 300mm wafers will be available from this quarter, and we are expecting five shipments in 2005 to major semiconductor device manufactures."

NEC reported front-end use of polymerised BCB to reduce k in copper metallisation structures earlier this year (Bulletin 538, June 23, 2004). Karl Suss, Dow Chemical and Fraunhofer IZM developed wafer level bumping and passivation IC packaging applications up to 2001 (Bulletin 386, June 13, 2001).

ASML is to install a full-field EUV pre-production tool at IMEC's 300mm research facility in late 2005 to prepare for a IMEC Industrial Affiliation Program on EUV lithography to begin in early 2006. The focus will be on the 32nm node and beyond to ensure that EUV technology is ready when the transition from 193nm immersion lithography takes place.

The programme will include investigation into optical path stability and monitoring; lithography reticle handling (including cleaning) and defect printability; assessment of line edge roughness (LER) and its relation to shot noise; resist assessment and process optimisation; 32nm node critical layer patterning; and printable defects of masks.

The programme details will be defined in collaboration with IMEC's core partners such as Infineon Technologies, Intel, Matsushita, Philips, Samsung and Texas Instruments, in the next six months. There is a growing consensus that 193nm immersion lithography will be introduced for 65nm half-pitch in 2007, and the outlook is positive for its extension to 45nm half-pitch. However, it will be very hard to get to the 32nm half-pitch since this would require very high-NA lenses and a high-index fluid.

"This agreement enables us to provide our partners with one of the world's first full-field EUV lithography tools," says Luc Van den hove, vice-president Silicon Process and Device Technology. IMEC invites semiconductor manufacturers, material suppliers, mask shops and peripheral lithography equipment suppliers to participate in the programme.

Toshiba has successfully signed-off a wireless design using Sequence's Multi-Threshold CMOS (MTCMOS) technology. MTCMOS power-gating works to reduce leakage currents by disconnecting the power supply from portions of the circuit when inactive. Leaking currents are prevented by inserting a series switch transistor between the logic cells and the power supply or ground. The switch is closed when the logic is operational and opened when the logic is inactive. Sequence and Toshiba have worked together to develop an automated process, based on Sequence's Physical Studio framework, to size and insert power-rail switching transistors. Reductions of 10x to 100x in leakage can be achieved by using this technique.

Shinichi Imai, senior manager of System LSI Design at Toshiba, comments:
"Sequence's innovative circuit design and automation techniques used on Toshiba's MTCMOS technology automatically reduced leakage currents while concurrent electrical checks ensured that the logic and signalling did not violate user-specified limits on key electrical parameters such as virtual ground voltages and currents."

Leakage control has become a major design issue due to currents that drain a battery's charge even when a wireless device is inactive or in standby mode. Transistors in each new process generation are leakier than those in previous generations (due to transistor scaling effects), only exacerbating the problem.

Leakage is also an issue in active mode. When the transistors are operational, any power wasted due to leakage is not available to be allocated to enhancing performance. Leakage also creates heat in high-performance devices raising operating temperatures. The Sequence power methodology includes fully automatic gate level power optimisation technology for the reduction of both dynamic and leakage power. The optimisations may be run independently or together with no adverse impact on area or timing. Sequence's MTCMOS approach uses patent pending optimisation algorithms designed to minimise area overhead and performance impact.

Cymer has selected a laser produced plasma (LPP) source as the most viable solution to achieve the high-volume manufacturing requirements for extreme ultraviolet (EUV) lithography processes at the 32nm node and beyond. EUV lithography is positioned for commercial deployment in 2009, but several challenges must be addressed to keep the technology on target. A key concern is to increase source output power to meet throughput requirements for high volume manufacturing, while remaining cost effective. Cymer has been developing EUV source technology since 1997.

Atmel's North Tyneside fabrication plant, in the North East of England, has just hit 50mn silicon chips per month capacity and is set to reach 60mn a month by the year end. The increased production is mainly in support of Atmel's Smart Card IC business. Atmel North Tyneside is also manufacturing microcontrollers for a wide range of industrial, consumer and automotive products. The fabrication plant also produces chips for mobile phone cameras, computers and other telecom products.

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