Process development
Ibis Technology claims a significant breakthrough in 300mm separation by implantation of oxygen silicon-on-insulator (SIMOX-SOI) wafer technology by substantially reducing the roughness of both the top surface of the wafer and the interface between the top-silicon and buried-oxide layers. Roughness values of less than 1Angstrom can now be achieved, representing a nearly four times improvement over previous results.
Ibis Technology provides oxygen implanters for the production of SIMOX-SOI wafers. The company believes that the improved wafers will meet or exceed the most demanding SOI wafer roughness specifications in the industry. The smoother features also may provide customers with better sensitivity on optical and laser-based measurement tools. SOI is a manufacturing technology where an insulating layer is created within a silicon wafer, isolating the top layer of silicon where the active transistors will be manufactured from the rest of the bulk silicon wafer.
The buried oxide layer acts as a barrier that reduces electrical leakage from the transistors, resulting in semiconductor devices that are faster and more power efficient. These benefits make SOI a valuable technology for chipmakers producing IC's for high performance applications such as servers and workstations, portable and desktop computers, wireless communication devices, integrated optical components and automotive electronics.
SIMOX uses an oxygen implanter to create a very thin insulating layer within the wafer, just below a thin layer of silicon on the top of the wafer. Ibis believes that, compared to competing technologies, the SIMOX process offers high quality SOI wafers at competitive costs in production quantities. The main and growing competing technology is wafer bonding (trapping silicon oxide) and cleavage (to create a thin silicon layer) using a hydrogen implant, as promoted by French company Soitec.
Cypress Semiconductor's Silicon Valley Technology Center (SVTC) says that it has become the first R&D services provider offering 65nm silicon processing capabilities to third-party companies. The centre has installed a 200-300mm wafer photolithography tool from ASML. The new TWINSCAN XT:1250, high numerical aperture (0.85), 193nm scanner will be available to established and start-up companies who are looking for advanced lithography capabilities on sub-90nm technology nodes. In addition to the litho cell, the processing cluster includes a resist coat-and-develop track, along with associated CD-SEM and overlay metrology tools. SVTC maintains a foundry-compatible toolset in a 1500m2 clean room in California.
