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News Article

SOI 65nm joint development

Freescale Semiconductor, Motorola's semiconductor spin-off, and TSMC have signed an agreement to jointly develop a new generation of silicon-on-insulator (SOI) high-performance transistor front-end technology targeted for the 65nm CMOS process node.
Freescale Semiconductor, Motorola's semiconductor spin-off, and TSMC have signed an agreement to jointly develop a new generation of silicon-on-insulator (SOI) high-performance transistor front-end technology targeted for the 65nm CMOS process node. The three-year agreement also provides TSMC with manufacturing rights to Freescale's 90nm SOI technology.

Freescale chief technology officer Dr Claudine Simson comments that TSMC is "a great partner through the joint development programme we have with Philips and STMicroelectronics in Crolles, France, near Grenoble."

Freescale has developed three generations of SOI technology since the mid-1980s. The company has shipped more than 7mn SOI-enabled products since it started production in 2001. It is currently establishing a 90nm CMOS SOI manufacturing platform in its Dan Noble Center facility in Austin, Texas.

The process will be used to make next-generation high performance networking and computing products. TSMC has been independently developing SOI technology starting from the 0.13micron node since the late 1990s.

During the joint development of the 65nm SOI high-performance transistor front-end technology, the two companies are expected to develop independently their own 65nm metallization back-end technology tailored to specific markets. Freescale will apply the overall technology to 65nm SOI chips at 300mm in the Crolles2 joint R&D and pilot manufacturing facility in France, which it shares with Philips and STMicroelectronics. TSMC may apply the technology in its Taiwan facilities, with a high-speed version that targets performance-driven applications in networking and computing, and a low-power version for handheld and portable applications.

SOI process technology allows transistors to switch faster than bulk CMOS, making it attractive for applications requiring high performance - higher speed and/or reduced power consumption. SOI enhances standard CMOS processes by using a silicon substrate with a buried insulating layer, isolating the active transistor elements. This lowers the capacitances between the silicon substrate and the active transistor area, and enables reduced power consumption, as well as higher speed for digital circuits. By using high-resistivity substrates, it also provides better isolation and reduced substrate losses, all factors desirable for radio frequency (RF) functionality.

Freescale was among the first in the industry to solve the technical challenges of SOI and enter volume production. The 65nm SOI high-performance transistor joint development project will be located at Freescale's Dan Noble Center.

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