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Process development

Samsung Electronics claims the industry's first 60nm 8Gbit NAND Flash memory device data storage for low-density mobile hard disks in mobile appliances.
Samsung Electronics claims the industry's first 60nm 8Gbit NAND Flash memory device data storage for low-density mobile hard disks in mobile appliances.

"NAND flash technology development continues to double density growth on an average of every 12 months," comments Dr Chang Gyu Hwang, president and CEO of Samsung Electronics' Semiconductor business. According to Hwang, densities have grown from 256Mbit in 1999, to 512Mbit in 2000, 1Gbit in 2001, 2Gbit in 2002 and 4Gbit in 2003.

Samsung's 8Gbit device meets the schedule for 2004. Samsung's 60nm process technology achieves an approximate 30% reduction in cell size over its 70nm 4Gbit NAND Flash memory developed last year. The result is the world's smallest 0.0082micron2 per bit cell size.

The company reports that key to the development is a 3-D cell transistor structure and high-dielectric gate insulating technology to minimise the interference between cells. The process also uses the older KrF lithography (248nm wavelength) rather than ArF (193nm) reducing bit cost by 50%, the company says. Samsung plans to introduce a new multi-level cell (MLC) technology in its 60nm process.

The 8Gbit NAND flash memory will allow designs of up to 16GBytes of storage on a single memory card - the space needed for up to 16 hours of DVD quality video or 4000 (five minutes per song) MP3 audio files.

Samsung expects to launch mass production of the 4Gbit NAND flash by Q1 2005. This year Samsung expects to double its volume of NAND sales and to account for 65% of the global market.

UMC has developed its first true embedded electrically erasable programmable read-only memory (EEPROM) based on a 0.25micron logic and mixed-signal platform. The embedded EEPROM targets the IC card market, including mobile SIM cards, debit cards, credit cards, ID cards, USB ID keys or any application where secure identification is required and information needs to be updated and programmed frequently. The EEPROM is based on a conventional two-transistor cell architecture with more than 500k program/erase cycles guaranteed.

UMC is planning to provide Silicon Shuttle prototyping services for the embedded EEPROM with the first scheduled to launch in November 2004. UMC is also in the process of developing 0.25micron embedded Flash, expected to become available by the end of 2004. Embedded Flash for 0.18microns and 0.13microns is scheduled for availability in 2005.

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