Alliances
As part of the technology and licensing pact, SUSS MicroTec will develop a complete line of 300mm and 200mm tools to enable commercialisation of C4NP.
For its part, IBM will continue advanced research and process optimisation of C4NP and offer on-site process training to customers who purchase commercial systems from SUSS MicroTec.
C4NP uses wafer solder bump technology, a semiconductor packaging technique which places pre-patterned solder balls onto the surface of a chip. These bumps ultimately carry data from individual chips to the rest of a computing system via a complex arrangement of intricate wiring and materials. C4NP allows the creation of pre-patterned solder balls to be completed while a wafer is still in the front-end of a manufacturing facility, potentially reducing cycle time.
The solder bumps can be inspected in advance and deposited onto the wafer in one simple step using technology similar to wafer-level bonding. The technology employs the simplicity of solder paste processing (stencil/screen), but instead uses pure molten alloy to produce the fine pitch capability of electroplating. Parallel processing allows increased efficiency and advanced quality control for wafer bumping.
C4NP also easily accommodates binary, ternary and quaternary alloys and minimises the recurring and additive costs of consumables since only the solder balls are created and transferred to the wafer without waste. C4NP is not dependent on wafer size, allowing 200mm and 300mm wafers to be processed with similar efficiency. Additionally, C4NP has achieved technical capability well beyond the International Technology Roadmap for Semiconductors (ITRS) specification for packaging technology, the companies report. Synopsys and Photronics are working together on a joint programme focused on improving the manufacturability and quality of advanced photomasks and reducing the cycle times for design-to-photomask flows. Synopsys and Photronics will jointly explore and develop solutions in the area of design for manufacturing (DFM) and mask synthesis, targeting faster time to yield for semiconductor manufacturers.
Specific activities include efforts to improve the design flow from layout to mask for alternating aperture phase shift masks (AAPSM), to increase the yield and cycle time for masks using strong resolution enhancement techniques (RET), and to reduce the turn around time for mask inspection using Synopsys' suite of DFM software tools.
Dan Page, vice president of engineering at Synopsys, comments: "We expect this will be one of a number of collaborations in which Synopsys will link its comprehensive DFM software solution to technology-leading manufacturers, such as Photronics, to advance the complex technological and business issues of chip manufacturing and ultimately enable our customers to achieve their production and yield goals."
Defence electronics specialist Thales and the French atomic energy commission CEA have formed a new joint laboratory to work on radio frequency micro electro mechanical systems (RF MEMS). It is hoped to use microelectronics and electro-mechanical functions to miniaturise certain critical microwave components while improving their performance.
The new laboratory brings together a CEA Leti team and a team from the Thales research centre at Orsay, France, which will join CEA Leti by the end of this year. The work will be based in Grenoble at CEA Leti's Heterogeneous Silicon Integration department and will have access to its dedicated microsystems development platform.
The laboratory aims to design and develop high-power microwave microswitches and integrated circuits based on these microswitches. Thales will use the microsystems developed in future radar and radio systems for the defence, security and aerospace markets and by other users in other fields. The laboratory will operate initially for a four-year period with a team of four permanent staff and two doctoral students. Funding support is provided through national and European contracts.
Acreo in Sweden is looking for partners where its capability for advanced and special-purpose surface treatment, chip mounting and wire bonding can be further exploited and advanced. Partners within the industrial or university R&D sectors are of interest Along with processing services, design and processing methodology and know-how is available for transfer to partners. The company is ready for co-operative efforts for development of new product or manufacturing technologies.
Acreo has roots in university R&D. The company offers its expertise and services in technology development and production of small series with short delivery cycles. Biosurfaces, used in biotechnical and biomedical applications, are of particular interest. The company has access to laboratory facilities for special purpose processing and treatment of surfaces, selective pattern generation, mounting of chips on carrier substrates and wire bonding of complex connection patterns. For the surface treatment, vapour phase equipment can be used to cover the surface with inorganic films and with most metallic materials. The Swedish company also can act as a manufacturer of special purpose micro-chip assemblies. http://www.acreo.se/
The Fraunhofer Institute of Integrated Systems and Device Technology (IISB) and SIGMA-C have incorporated "smart decomposition simulation" capabilities into SIGMA-C's SOLID lithography simulator. The new algorithm combines Real Exposure over Non-topography and Flood Exposure over Topography (RENFT) simulations based on a decomposition of the full simulation developed by Dr Andreas Erdmann and his lithography simulation group at the IISB in Erlangen, Germany. The integration of the new algorithm into the SOLID-C software package enables the efficient simulation of many critical wafer topography scenarios, such as resist footing effects in the vicinity of poly-Si lines on patterned wafers. The SOLID-C suite of topographical (or 3D) photomask simulation has more than three years of production acceptance at integrated device manufacturers (IDMs) worldwide. Simulation speed for the new products has been increased more than 10x over other wafer topography scenarios. Memory requirements are also substantially reduced.
Molecular Imprints (MII) has opened a European office in Aalen, Germany. MII develops step and flash (S-FIL) imprint lithography. The new office will offer technology and applications support for regional customers and for MII's exclusive European distributor, Carl Zeiss NTS. In conjunction with MII's new office, Carl Zeiss NTS is building an Applications Laboratory at its Oberkochen facility.
Silicon Genesis (SiGen) is to outsource all of its 200mm silicon wafer implant requirements to INNOViON and introduce INNOViON as their preferred implant service provider to licensees of SiGen technologies. Gary Holyoak, INNOViON president and CEO, comments: "This partnership has evolved over the years as we worked closely with SiGen to refine and provide the implant process needed to successfully develop their silicon-on-insulator (SOI) substrate technology. With our expertise - advanced tooling and process techniques for implanting hydrogen - we believe we are uniquely positioned to support the sustained growth anticipated in SOI manufacturing."
Rohm and Haas Electronic Materials and UP Chemical have made Hi-k Grade aluminium and hafnium precursors for high-k dielectric films commercially available. Rohm and Haas Electronic Materials will use UP Chemical's proprietary technology to manufacture the Hi-k Grade products. The two companies will co-ordinate quality assurance efforts to ensure global availability of the Hi-k Grade precursors. A 1998 investment agreement made Rohm and Haas the global supplier of UP Chemical's technologies beyond Korea. UP Chemical specialises in DRAM and high-k gate dielectric precursors based on aluminium, hafnium, tantalum and titanium.
