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Investment & Expansion

Canon and Toshiba have agreed to establish a joint venture in October 2004 for the development, production and marketing of next-generation flat-screen "surface-conduction electron-emitter display" (SED) panels.
Canon and Toshiba have agreed to establish a joint venture in October 2004 for the development, production and marketing of next-generation flat-screen "surface-conduction electron-emitter display" (SED) panels.



The SED is a new type of flat-panel display technology, created through the merging of Canon's proprietary electron-emission and microfabrication with Toshiba's cathode-ray-tube (CRT) technology and mass-production of liquid crystal displays and semiconductors.



Like conventional CRT televisions, the SED uses the collision of electrons with a phosphor-coated screen to emit light. Electron emitters, which correspond to an electron gun in a CRT television, are distributed in an amount equal to the number of pixels on the display. In addition to high brightness and high definition, the SED delivers exceptional overall image quality in terms of fast video-response performance, high contrast, high gradation levels and low power consumption.



Canon began research in the field of SED technology in 1986. Joint development with Toshiba began in 1999 to commercialise SEDs. Plans for the new joint venture company call for the commercialisation of SED panels primarily for large-screen flat-panel televisions, with production scheduled to begin in 2005. Following the initial launch, a mass-production factory will be readied and production volume will be increased.



Lattice Semiconductor will advance $125mn to support Fujitsu's new 300mm silicon wafer fab being constructed in Mie, Japan. The advance payment will be made in four stages, based upon the successful completion of specific milestones, with a $25mn payment scheduled for October, 2004, and the balance anticipated to be paid by Q2 2006. All advances will be repaid in the form of future delivery of production wafers to Lattice.



Fujitsu's new 300mm fab is scheduled for completion in Q2 2005. Lattice will initially gain 90nm technology for its next-generation field programmable gate array (FPGA) products in late 2005. Fujitsu has designed its 90nm technology to be easily scaleable to 65nm. Lattice has also extended its agreement with Fujitsu to 300mm/65nm wafers and technology from the new fab.



Lattice and Fujitsu made an initial announcement of co-operation in March of this year. At that time, it was announced that Fujitsu would supply Lattice with leading-edge 130nm and 90nm CMOS process technologies, as well as a 130nm technology with embedded Flash memory being jointly developed by Fujitsu and Lattice. That deal covered 200mm wafer production for all three technologies.



Fujitsu already manufactures products using 90nm CMOS technology on 200mm wafers at its Akiruno Technology Center, located in western Tokyo, including initial silicon for Lattice's next-generation, high-end FPGAs, the LatticeSC (System Chip) product. In addition, 130nm technology from the Mie facility is currently supplying initial production quantities of Lattice's low-cost FPGA products, the LatticeECP-DSP (EConomy Plus - DSP) and LatticeEC (EConomy) devices, as well as development wafers for the LatticeXP non-volatile, infinitely reconfigurable Flash-based FPGAs.

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