Process development
The 65nm process technology also includes several unique power-saving and performance-enhancing features. These include an enhancement of the strained silicon technology first implemented on Intel's 90nm process technology. The second generation strained silicon increases transistor performance by 10-15% without increasing leakage. Conversely, these transistors can cut leakage by four times at constant performance compared with 90nm transistors. As a result, the transistors on Intel's 65nm process have improved performance without significant increase in leakage (greater electrical current leakage results in greater heat generation).
The reduced 35nm gate length and 1.2nm gate oxide thickness combine to provide improved performance and reduced gate capacitance. The reduced gate capacitance ultimately lowers a chip's active power. The new process also integrates eight copper interconnect layers and uses a "low-k" dielectric material that increases the signal speed inside the chip and further reduces chip power consumption.
Intel has also implemented "sleep transistors" in its 65nm SRAM. Sleep transistors shut off the current flow to large SRAM blocks when they are not being used, which eliminates a significant source of power consumption on a chip. This feature is especially beneficial for battery-powered devices, like laptops.
Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group, reports: "We have taken a holistic approach by developing solutions that involve systems, chips and technologies, and include innovations on our 65nm technology that go beyond simply extending prior techniques."
Intel's 65nm semiconductor devices were manufactured at the company's 300mm development fab (D1D) in Hillsboro, Oregon, where the process was developed. More information on Intel's 65nm logic technology will be presented in a paper at the IEEE International Electron Devices Meeting in San Francisco, December 12-15, 2004.
US R&D centre ATDF reports that it has successfully demonstrated process capability for 45nm multi-gate field effect transistors (MuGFETs) with help from the TestChip division of HPL Technologies. The partners hope the device could replace conventional CMOS transistors and that, if proven, MuGFETs could be introduced into manufacturing within several years, although integration schemes remain to be developed. ATDF has been working at the 45nm node and below for more than a year. The MuGFET demonstration was part of a custom development programme involving a device maker, a university, and equipment, substrate and materials suppliers. HPL supplied test chip creation infrastructure and project management.
The demonstration completes the first phase of the ATDF's effort to identify manufacturing problems associated with MuGFET fabrication on silicon. Additional programme phases will address manufacturing issues such as threshold voltage (Vt) roll-off that emerged in experiments leading to the demonstration. With the successful completion of the first phase, the test chip is now available from ATDF for any company needing access to the technology.
