Process development
"Boron diffusion has traditionally been a major problem in both silicon and silicon-germanium devices, having a significant impact on the scalability of MOS and bipolar technologies," comments Innos director Peter Ashburn. In SiGe heterojunction bipolar transistors, boron diffusion limits the achievable basewidth and therefore degrades the high frequency performance of the transistor. In the halo region of a metal-oxide semiconductor field-effect transistor (MOSFET), it degrades the abruptness of the source/drain extension profiles and hence worsens short channel effects. The problem is exacerbated by transient enhanced diffusion, in which increased diffusion is experienced when dopant implants are annealed. Innos has expertise in silicon, microsystems (MEMS) and other nanotechnologies.
No surprises have emerged to prevent the introduction of 193i for 65nm half-pitch in 2007, according to International SEMATECH's international symposium on immersion and 157nm lithography. The outlook is also positive for its extension to 45nm half-pitch and possibly below. Potential solutions for achieving the latter include hyper-numerical aperture, improved lens design, high refractive-index fluids, high-index resists and lens material, double exposure, and related infrastructure. Equipment suppliers ASML, Nikon and Canon forecast first-generation production tools in 2005, and second-generation exposure equipment in 2006. Also, manufacturers' experiments on prototype tools confirmed key aspects of lithographic performance, including process window and critical-dimension (CD) uniformity.
Development of 157nm lithography continues, but at a reduced level. Japan's Selete consortium is installing a 157nm scanner to lead infrastructure development. In addition, there are global efforts toward 157nm immersion, although eventual insertion of that technology remains an open question. "Excellent progress" has been demonstrated on a Czochralski process (CZ) growth method for the calcium fluoride lenses used in 157nm scanners.
Installation of the world's first 193nm pre-production immersion lithography system for 300mm wafers has been completed at Albany NanoTech's College for Nanoscale Science and Engineering (CSNE) in New York State. The qualification process has also begun. The activity brings together ASML, IBM, and Tokyo Electron (TEL). The integrated platform consists of two components: the ASML TWINSCAN AT:1150i scanner, and a TEL CLEAN TRACK LITHIUS coater/developer system. AMD and Infineon will also work with IBM and CNSE in the use of the AT:1150i for the development of immersion lithography processes and applications.
The US Semiconductor Research Corporation (SRC) is collaborating with UMC on its first International Fellowship Award outside of the USA. The SRC International Fellowship Program will provide full tuition and fees to one international student a year and is renewable for up to five years with the total sum for each student reaching as much as $100,000. In addition, the department within which the student is studying receives a gift of $2000 per year.
This year's recipient is Feng Yuan, a graduate student in Electrical Engineering at National Taiwan University. Yuan also received his Baccalaureate Degree from NTU in 1997 and has a number of technical publications to his credit. His doctoral research is in the area of silicon germanium (SiGe)-based high mobility heterostructures, funded by UMC through SRC's Research Customisation Program. Yuan's specific interest is in strained silicon devices, SiGe heterojunction bipolar transtors (HBTs), and their circuit applications. The Fellowship begins with the autumn 2004 term and will extend for a one-year period.
