News Article
Matrix uses 3D technology to make smallest one-gigabit memory chip
US fabless chip maker Matrix Semiconductor has produced what it claims is the world’s smallest one-gigabit silicon memory chip.
US fabless chip maker Matrix Semiconductor has produced what it claims is the world’s smallest one-gigabit silicon memory chip.
Measuring just 31mm2, the ground breaking three-dimensional memory was manufactured using two new technology breakthroughs - hybrid scaling and segmented wordline architecture.
Using these techniques, the company has within just one year been able to double the amount of memory capacity it can cram into the same area of silicon semiconductor.
Hybrid scaling allows different resolutions of feature sizes to be incorporated into the layers of a 3D chip.
Using an existing 180nm toolset, the base logic layers of Matrix’s new memory chip were manufactured at 150nm while subsequent memory layers were at 130nm.
The beauty of this is that it allows a greater number of memory bits to be placed on top of the logic array than is possible using conventional techniques.
The company’s patented segmented wordline architecture meanwhile minimises that the area of silicon taken up by non-memory logic circuitry by separating the memory and logic circuitry into different layers.
This results in a far more efficient use of silicon, reducing the die's area by nearly 25%.
Measuring just 31mm2, the ground breaking three-dimensional memory was manufactured using two new technology breakthroughs - hybrid scaling and segmented wordline architecture.
Using these techniques, the company has within just one year been able to double the amount of memory capacity it can cram into the same area of silicon semiconductor.
Hybrid scaling allows different resolutions of feature sizes to be incorporated into the layers of a 3D chip.
Using an existing 180nm toolset, the base logic layers of Matrix’s new memory chip were manufactured at 150nm while subsequent memory layers were at 130nm.
The beauty of this is that it allows a greater number of memory bits to be placed on top of the logic array than is possible using conventional techniques.
The company’s patented segmented wordline architecture meanwhile minimises that the area of silicon taken up by non-memory logic circuitry by separating the memory and logic circuitry into different layers.
This results in a far more efficient use of silicon, reducing the die's area by nearly 25%.
