Process development
Direct-tunneling RAM uses a very thin (~1.5nm) oxide Flash structure in which charge can be stored on either a floating gate or on a charge-trapping layer. In both cases, the use of high-k materials is being considered as well to lower the write/erase voltages. First simulation results of the expected threshold voltage window for different combinations of voltages and tunnel oxide thicknesses, as obtained from IMEC's tunneling model, suggest a 10ns programming time at the 45nm node.
Ferroelectric field effect transistors (FeFET) have recently regained a lot of attention because of its superior scalability compared to capacitor-based ferroelectric RAM. Also here, the advantage of using high-k materials is substantial since they can be used as a buffer layer between the channel and the ferroelectric to lower write/erase voltages. The floating body cell is based on the memory effect in silicon-on-insulator (SOI) devices initially developed at IMEC as far back as 1988. The technology is being adapted for planar as well as FinFET device structures.
Preliminary retention results, obtained on partially depleted SOI MOSFETs programmed by impact ionisation, show the memory effect in scaled-down SOI technology. In all of these cases, IMEC has a longstanding background and expertise guaranteeing that results can be generated within a very short time frame of six to 18 months. The eRAM project complements IMEC's Flash memory project started in 2000.
Fast first-level cache memory has been (and probably will continue to be) addressed by static RAMs, but these devices are reaching their scaling limits due to a drastic increase in relative cell size. Since most IC applications (microprocessors, systems-on-chip, telecom...) will need relatively large amounts of on-chip memory, their footprint is expected to increase to 80-90% of the chip area in some of these applications. At the same time, embedded dynamic RAM has never been widely accepted as a mainstream technology option because of limited availability, process complexity and cost issues.
The technology that is being developed within IMEC's programme neither aims to replace the first-level cache (SRAM), nor the (eventual) embedded non-volatile Flash or read-only memory (ROM) blocks. The eRAM and Flash Memory IIAPs will be part of IMEC's newly established Advanced Memory programme.
BOC Edwards has established a joint development programme with the IMEC European research centre in Belgium. The programme focuses on the application of supercritical CO2 (scCO2) cleaning processes for the manufacture of next-generation semiconductor devices. BOC Edwards has shipped an integrated supercritical CO2 processing system, including its DFP 200 high-pressure, single-wafer process module to IMEC. This supercritical CO2 technology demonstrator will be used in a three-year process development programme.
The application of scCO2 for all process steps where the use of water needs to be avoided will be assessed. The will start with the investigation of the use of scCO2 for the cleaning of advanced porous low-k materials. The low viscosity and surface tension of scCO2 allows for efficient cleaning of small feature sizes.
Applied Materials has introduced electrochemical mechanical planarisation (Ecmp) capability on its Reflexion LK platform. The company claims the system as the industry's first and only CMP tool to provide this high-performance, cost-effective and extendible solution for copper/low k manufacturing at 65nm and beyond.
The Ecmp process removes bulk copper at a high rate (greater than 6,000Angstroms/min.) by electric charge, independent of downforce. The aim is to planarise fragile ultra-low-k films with minimal dishing, erosion and defects (less than 0.1/cm2 on a dual damascene structure). A low cost electrolyte chemistry replaces expensive copper slurry, the company says. The thin, uniform, copper film and barrier/liner materials that are left can then be efficiently removed at very low down force (less than 1.0psi).
Dr Ming Xi, general manager of the company's Planarisation and Plating group, comments: "The Applied Reflexion LK Ecmp system achieves all of these challenging goals while improving throughput up to 25% and reducing operating cost up to 30% compared to conventional copper polishing systems."
