Packaging
The device will be first incorporated into a wearable wireless electroencephalogram (EEG) developed by IMEC and the University Hospital Leuven, Belgium, last year. Using the 3D SiC, patients can wear a comfortable device and maintain maximum mobility during the electroencephalogram, eliminating the hospital stay traditionally required for this procedure.
The system-in-a-cube (SiC) was developed as part of IMEC's Human++ programme, which envisions similar SiCs as sensor nodes constituting a body area network (BAN). The BAN will be used to gather vital body information into a central intelligent node, which in turn will communicate wirelessly with a base station. Such BANs require a number of small low-power intelligent wireless nodes with sufficient computing power, wireless capabilities and integrated antenna.
The Human++ programme combines experience and expertise in wireless communications, packaging techniques, energy scavenging technologies and low-power design techniques. Current work focuses on the complete integration of the wearable wireless EEG prototype in the 1cm3 SiC and is expected to be finalised in October this year.
This first 3D-stack prototype integrates a commercial low-power 8 MIPS (million instructions per second) microcontroller and a 2.4GHz wireless transceiver, crystals and necessary passive devices, as well as a custom-designed matched dipole antenna.
Each layer of the 3D stack connects to its neighbouring layers through a dual row of fine pitch solder balls. The bottom layer has a BGA (ball grid array) footprint, allowing standard techniques for module mounting.
The tasks of the microcontroller unit range from adjusting sensor preamps and digitisation to data interpretation, forward error coding and media access control (MAC) implementations from low to medium complexity. The 12 bit microcontroller ADC (analogue to digital converter) provides enough dynamic range for most sensors to be directly interfaced with the module. The stacking feature even allows a specific sensor to be integrated into a single layer, resulting in an application-specific cubic sensor module.
Future developments will mainly focus on further size reduction and the integration of IMEC's low-power processing, wireless and power-scavenging technology. Adding an extra stack layer with solar cells and energy-storage circuitry will offer a complete standalone solution.
ChipPAC is developing a proprietary "Package-in-Package" (PiP) stacking technology for cell phone applications. PiP stacks a fully tested internal stacked module (ISM) on top of a base assembly package (BAP) and interconnects them with wire bonding and moulds into one standard chip-scale package (CSP).
The ISM is a standard land grid array (LGA) that can stack multiple memory chips like Flash (NOR/NAND), SDRAM and SDR/DDR. The BAP is a standard ball grid array (BGA) which can be a single ASIC chip or a stack of ASIC, analogue or other chips.
ChipPAC is developing the first member of this family of packages for a major DSP supplier for cell phone applications. Also in collaboration with the customer and two major memory suppliers ChipPAC is driving the standards for the ISM including physical dimensions, and electrical and mechanical specifications.
Dennis McKenna, chairman and CEO of ChipPAC, comments: "Die stacking to date has been primarily with memory-to-memory devices. As we look to stack logic and many types of memory, with different wafer-fab sources, processes and die shrinks, we will face greater manufacturing risks. Package-in-Package reduces these risks. The stacking of pre-tested packages allows for design flexibility, competitive sourcing and shorter time-to-market, with minimum risk versus the alternatives of SOC (system on chip) or die stacking."
Typical profile is 15x15x1.4mm with more than 500 solder balls at 0.5mm pitch.
