Malaysia foundry takes up IMEC 0.13micron process
The Silterra Malaysia foundry and the IMEC European R&D centre have signed an agreement for a joint development project (JDP) with the intention of creating a foundry-compatible 0.13micron CMOS process technology. The process will be based on IMEC's 0.13micron platform and modified to meet the requirements of wafer foundry customers.
Bruce Gray, chief operating officer and interim CEO of Silterra, reports:
"We have already completed the groundwork with customers to define their technology requirements and understand their specifications."
A team of Silterra and IMEC engineers will fine-tune the base-IMEC process at IMEC's research facility in Leuven to meet the specifications provided by Silterra. The process will have physical design rules and electrical characteristics that match mainstream technologies to meet the needs of customers with a multi-foundry sourcing strategy. The technology will have FSG (fluoro-silicate glass) or low-k inter-metal dielectric options and up to eight layers of copper interconnect.
The new process, like Silterra's own foundry compatible 0.18- and 0.22-micron logic technologies, is targeted at a wide range of products for communications, consumer and computational applications. Silterra expects to provide supporting design libraries and IP in Q1 2005, with pilot production starting in Q2 2005.
In an obviously related move, Silterra Malaysia has placed a "large order" with Applied Materials for systems to manufacture 0.13micron copper-based chips. The order includes Applied's dielectric deposition, etch, barrier/seed, electrochemical plating and chemical mechanical polishing systems - as well as its defect inspection and SEM/FIB defect analysis systems. Equipment installation is scheduled to begin in Q3 2004 with qualification completed in Q1 2005.
