+44 (0)24 7671 8970
More publications     •     Advertise with us     •     Contact us
*/
News Article

VLSI II: High-speed conversion, 65nm

More companies reported results given at the 2004 Symposium on VLSI Technology in Hawaii.

More companies reported results given at the 2004 Symposium on VLSI Technology in Hawaii.

Infineon highlighted a high-performance 4GSamples/s 6bit flash analogue-digital converter ADC with 8bit output realised in a 0.13micron standard CMOS technology. The outputs of the 255 small-area comparators are averaged by a fault tolerant thermometer-to-binary converter. The ADC also uses an on-chip low jitter VCO (voltage controlled oscillator) for clock provision and consumes 990mW at a single supply voltage of 1.5V.

High data transfer rates are needed in various serial communication applications such as the read channels of hard disks that rely on digital signal processing circuitry. These circuits require high speed ADCs to provide the interface between the analogue and digital parts of the system. It is desirable to realise these integrated circuits in standard CMOS technologies to allow low cost production and monolithically integration of ADC and digital signal processor (DSP).

In a classical n-bit Flash ADC only 2n-1 comparators with low input offset voltages are used to generate a perfect bubble-free thermometer code at the output of the comparator bench. To guarantee the demanded low input offset voltage, large active device areas must be used to reduce the effect of device mismatch within the comparators.

In contrast to this traditional approach, the new Infineon ADC with 6bit linearity uses 255 comparators with small active area. As a consequence, the input offset voltages are in fact higher, and a bubble-free thermometer code at the output of the comparator bench is not obtained, but the small sized comparators can be optimised for maximum operation speed.

In high-speed ADCs (>1GS/s), clock generation and distribution is a crucial point to meet the desired resolution. Since an uncertainty of the clock signal (jitter) directly translates into a reduction of the resolution of the system, the jitter has to be kept as small as possible. At an input frequency of 1GHz, a 6bit ADC needs to be clocked with a jitter of less than 1ps. Therefore, the new ADC comprises an on-chip LC oscillator with low jitter, which provides a complementary sinusoidal signal at a frequency of 4GHz.

Since only standard digital transistors are used, the ADC can easily be monolithically integrated in a signal processor without the need for analogue process options. Furthermore, the RF clock signal is generated on-chip and only a single supply voltage of 1.5V is used. Infineon also presented papers on magnetic and ferroelectric memories and analogue CMOS along with a review of "Multi Gate Transistors and Memory Cells for Future CMOS" (invited paper).

NEC has succeeded in the development of multi-level Cu/Low-k interconnects for second generation 65nm-node VLSIs. By improving the interconnect structure and dielectric material, reduction of the effective dielectric constant (keff) to the target value of 3.0 was successfully demonstrated, without degrading reliability. In addition, interconnect power consumption was reduced by 15% and signal speed was improved by 24%, as compared with conventional structures. The porous low-k dielectric layers have sub-nanometre pores.

A plasma-polymerised BCB (p-BCB) film, developed by NEC, was used as the pore sealing film. Since the p-BCB film has strong resistance to Cu diffusion as well as relatively low k-value, the barrier metal can be extensively thinned. Consequently, using the DD pore sealing technique, line resistance and via resistance were reduced by 9% and 75%, respectively.

NEC has adopted a structure in which the line trenches and via holes are simultaneously filled with copper. Compared with the single damascene structure, where the line and via are formed independently, the parasitic capacitance of the DD structure was reduced by 10% due to a decrease in the number of capping dielectrics with relatively high k-value. An etching technique was developed to reduce plasma damage to the low-k films.

×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: