+44 (0)24 7671 8970
More publications     •     Advertise with us     •     Contact us
*/
News Article

16Mbit magnetic memory record

Infineon Technologies and IBM claim the world's first 16Mbit magnetoresistive random access memory (MRAM).

Infineon Technologies and IBM claim the world's first 16Mbit magnetoresistive random access memory (MRAM). The new non-volatile memory chip is said to be the highest density MRAM reported to date. The companies believe that the achievement demonstrates the potential of MRAM to become a universal memory for high performance computing and mobile applications.

It is claimed that MRAM is faster and consumes less power than existing technologies. The time required to write the first bit of information into an MRAM chip is about 1mn times faster than the time required for a Flash memory chip, the companies say. The time required to read the first bit of information out of an MRAM chip is about three times faster than a NOR Flash chip and about a factor of 1000 faster than in a NAND Flash chip. Additionally, MRAM requires much less power in comparison to DRAM technology.

The 16Mbit MRAM product demonstrator is realised in a 0.18micron logic based process technology. It uses a 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell and features an SRAM-like interface which is prevalent in mobile and handheld applications and well suited to the operation of the MRAM core, the companies say.

The chip was designed to operate at access and cycle times of 30-40ns. Among published multi-Mbit MRAMs, this new MRAM chip claims the highest density (16Mbit) with a cell size of 1.42micron2. The multi-Mbit MRAM design also uses a novel bootstrapped write driver circuit and several design features to reduce standby current.

The 1T1MTJ MRAM cell has three metal layers: ground mesh, write word line (WWL) and bit line (BL). Only three MRAM-specific levels (VA, MA, MTJ) are required beyond the three-Cu-level CMOS base technology. The low resistance ground mesh allows large uninterrupted arrays. The chip is divided into two 8Mbit units, each of which is split into 64 128kbit blocks. Each 128kbit block contains a single array and associated circuits.

×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: