Companies presented their research at the 2004 Symposium on VLSI Technology

STMicroelectronics claims "significant progress" in developing a replacement for Flash memory. Many companies are working on the phase-change memory (PCM) that potentially offers better performance than Flash. The most important feature of PCM is better potential for scaling to smaller feature sizes.

Three years ago, ST reports, it concluded that the PCM technology of Ovonyx could be adapted as a semiconductor memory technology. The material is already used in re-writable CDs. In 2001, ST licensed the technology, also known as Ovonic Unified Memory (OUM), from Ovonyx and the two companies set up a joint-development team, largely based in Agrate Brianza, near Milan, where ST's world wide non-volatile memory (NVM) development is based. Intel is also working with Ovonyx on the technology in an independent agreement.

The chalcogenide materials used in PCM can be reversibly switched between two stable states - one amorphous with a high electrical resistance, the other crystalline with a low resistance - by appropriately heating the material. A chalcogen is any material that contains sulphur, selenium, or tellurium (three elements that have closely related chemical properties) - in ST's new technology, tellurium plays the key role. A PCM cell consists essentially of a variable resistance formed by the chalcogenide material and its tiny electrical heater, along with a selection transistor used for the read/write operations.

In one paper at the symposium, ST presented a cell structure that can be integrated into mainstream chip manufacturing processes, along with indications of its manufacturability and cost. In a second paper, ST described the practical implementation of the technology in the form of an 8Mbit demonstrator chip designed to assess the feasibility of cost-effective large non-volatile memories.

Based on the highly-promising results it has obtained to date, ST already envisages PCM memory being used in medium-density, stand-alone memories and embedded applications. Moreover, by demonstrating the feasibility of the key features that make the PCM cell most attractive, ST has increased its confidence in the long-term scalability of the technology with the prospect of its becoming a mainstream non-volatile memory.

Specialists currently see barriers to pushing Flash memory technology beyond about 20nm. The problem arises because Flash depends on a high voltage (about 20V) for write/erase operations. Insulating barriers that can sustain these levels of potential difference need to be a certain thickness - any smaller and charge leaks out losing the memory value, any thicker and the write/erase voltage increases further.

Flash memory has been one of the industry high points in the last year or two, being one of the fastest growing sectors. ST estimates that the Flash market will show a compound annual growth rate (CAGR) of 19% over the 2003-2008 period. In the ten years from 1990 to 2000, the size of an individual Flash cell was reduced by a factor of 30.

Renesas Technology has developed a new static random access memory (SRAM) cell type that uses a DRAM capacitor to give an approximately 4-digit reduction in soft error rate compared with previous products made on 0.13microns, together with greatly decreased cell size and lower power consumption. Alpha ray radiation experiments have been used to confirm the performance. The company has named the technology superSRAM and the process will be put into commercial production for 16Mbit low-power SRAM mobile applications.

Renesas' 0.98micron2 SRAM cell combines thin-film transistors (TFTs) and a DRAM capacitor on a 0.15micron process. The cell size is less than half that of the company's current CMOS-based 0.15micron process SRAM. In addition, a data retention current of less than 1microA has been achieved.

Unlike a pseudo-SRAM that employs DRAM memory cells, the new SRAM cell does not need refresh operations. A typical pseudo-SRAM standby current is 100microA. That allows an approximately double-digit improvement in data retention current compared with a pseudo-SRAM, for lower power consumption in mobile applications. Higher performance and a smaller cell area have been achieved without using special processes. A conventional CMOS-based SRAM is characterised by a cell area at least ten times larger than that of DRAM using the same process rule, and has an extremely large chip area compared with DRAM.

Process scaling brings a reduction in the capacitance of memory cell storage nodes leading to the occurrence of soft errors, causing loss of information due to charges generated when the silicon substrate is irradiated with alpha or neutron rays. When further lower power consumption is implemented, lower supply voltage results in an accelerated decay in the amount of charge accumulated at storage nodes. This makes soft errors an even greater problem with regard to product reliability. Preventing this problem requires the adoption of measures such as sacrificing chip area to increase node capacitance or the provision of error correction (ECC) circuitry.

Normal SRAM cells consist of six transistors: two CMOS type load MOS transistors, two access MOS transistors and two driver MOS transistors. In the new superSRAM, the two load MOS transistors are replaced by two TFTs located above the access MOS/driver MOS transistors and two cylindrical capacitors stacked on top of the node. A sub-1micron2 cell size was previously considered only to be attainable with 90nm processes. As with conventional SRAM, information stored in a memory cell is automatically maintained by means of the load and driver transistors, so that there is no need for the refreshing operations of DRAM. Following on from the 16Mbit model, there are plans for commercial development of 32Mbit superSRAM during the current fiscal year.

Toshiba unveiled a high-performance metal-oxide semiconductor field-effect transistor (MOSFET) and advanced multi-layer wiring technology aimed at 45nm processing.

The new ultra-thin gate oxide film has an equivalent oxide thickness (EOT) of less than 1nm thick and realises a 1.5-order reduction in current leakage over conventional SiON film. The MOSFET achieves a drive current of 820microA/micron for the NMOSET, and of 300microA/micron for the PMOSFET at 0.85V (Ioff=50nA/micron).

The new wiring technology optimises parameters in terms of operating frequency and power consumption suited to 45nm generation products. The new technology demonstrates a 130nm pitch of the first metal layer - a 72% shrink from the 65nm generation.