Investment & expansion
Elpida Memory and its Hiroshima subsidiary have started construction on a second 300mm wafer fabrication facility. Hiroshima Elpida's first 300mm facility will also expand its production capacity. The new facility is due to begin mass production during H2 2005. Elpida will introduce 85nm processing at the site later that year.
The construction area is some 23,000m2 with a gross floor space of 91,000m2 - almost double the size of the existing facility. Elpida plans to expand the production capacity of the new facility in several stages leading up to a maximum capacity of 60,000 300mm wafers per month. The total construction cost is estimated at JPY450-500bn ($4.1-4.5bn). Hiroshima Elpida's first 300mm facility is currently engaged in the test and mass production of semiconductor products, and Elpida plans to increase its production capacity from 22,000 wafers per month to 28,000 wafers per month during H2 2004.
The facility, which began operation in January 2003, primarily manufactures high-density DRAM products for the server market. However, there are future plans to manufacture 1Gbit DDR2 SDRAM products as well as Mobile RAM devices for cellular applications and 0.11micron digital consumer DRAM devices. Elpida is a joint venture company formed by NEC and Hitachi in December 1999 and has been in operation since April 2000.
US semiconductor research and development funding currently falls short of what is needed to keep up with the International Technology Roadmap for Semiconductors (ITRS) by $1.5bn, according to Dr John Kelly III, senior vice-president and group executive of IBM Technology.
"The price of not starting now on a massive, co-ordinated research and development effort in nanoelectronics could be nothing less than a loss, in just two decades of US economic and defence leadership," said Kelly at a US Semiconductor Industry Association (SIA) "Leadership Luncheon".
In response to the industry challenge, the SIA has called for the creation of a US Nanoelectronics Research Institute (NRI) to meet the needs of furthering an industry that currently depends on CMOS. This technology has an expected future lifespan of 15 years at most, according to many accounts of CMOS' physical limits.
Kelly added that the $1.5bn shortfall does not include what is needed to prepare for the post-CMOS era. The new NRI would be charged with generating new ideas and discoveries along with demonstrating the feasibility of any new switching, memory and interconnect technologies by 2020.
