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Process development

Samsung Electronics claims the industry's first "CVD aluminium" 70nm DRAM process technology. The aluminium chemical vapour deposition (CVD) process technology forms conducting films by turning aluminium metal-organic source materials into particles through chemical reactions, depositing them on the wafer surface.

Samsung Electronics claims the industry's first "CVD aluminium" 70nm DRAM process technology. The aluminium chemical vapour deposition (CVD) process technology forms conducting films by turning aluminium metal-organic source materials into particles through chemical reactions, depositing them on the wafer surface.

Existing DRAM circuit-wiring processes use physical vapour deposition (PVD), in which thin films are formed by turning solid-state materials into particles. However, "voids" in the metal from non-uniform deposition on the wafer surface causes problems in making reliable electric circuits. This has made PVD difficult to apply in 90nm-or-less processes.

The CVD aluminium process technology can solve both the void problem and dramatically improve the circuit properties. Samsung believes that it is an essential process technology for manufacturing 70nm DRAMs. Samsung's analysis further suggests that it would reduce costs related to circuit-wiring processing by up to 20%, as it does not require the planarisation, etch-back or cleaning processes previously needed.

The company has applied for 15 international patents related to this technology. Samsung Electronics has already produced 90nm 512Mbit DRAM samples by applying aluminium CVD and plans to unveil 70nm DRAM that uses this process technology by the end of the year.

eASIC has taped out its first structured ASIC array to be fabricated by a European integrated device manufacturer (IDM) partner on a 0.13micron process. The taped-out array called FA1 is the smallest member of the company's Structured eASIC product family. The initial parts will be used to characterise timing and power for the structured ASIC fabric and cell libraries.

The complete product family is scheduled for released to production in early Q1 2005. The company has previously produced validation chips at STMicroelectronics. This product is being co-developed with Flextronics Semiconductor who will also be offering structured ASIC products and services.

eASIC developed its Structured eASIC to consist of an array of logic cells (eCells) with SRAM based look up tables (LUTs) and flip-flops. The eCells are inter-connected by a segmented wiring grid using upper metal layers that are customised per customer design with a single via-mask. Logic programming of the eCell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device.

A customer design is implemented on the Structured eASIC fabric by using a combination of a bit-stream to program the LUTs and a single custom via-mask to customise the routing. Via-customisation can also be performed by direct-write e-beam lithography, avoiding soaring mask costs for small runs.

The FA1 has 600k usable ASIC gates, 372 I/Os and four phase-locked loops (PLLs). Target gate speeds are for a fast input to output of 60ps and an average gate delay of 80ps. Operating frequencies are put at 400MHz with power consumption rates at 20nW/MHz/gate. Typical system power is quoted as 350mW.

Seiko Epson has completed development work on a one-chip, 8bit microcontroller with integrated EEPROM and resistance-to-frequency type A/D converter for radio-frequency (RF) tags used in temperature and humidity monitoring applications.

Attaching an external resistor and a thermistor or humidity sensor to the S1C8E108 device enables the unit to measure temperature and humidity. The resistance-to-frequency type A/D converter allows readings to be taken with minimal power draw. A built-in unsigned integer multiplication and division circuit allows complicated arithmetic processing to be achieved with low load. Current consumption at 3V with 4MHz operation is typically 1.6mA. Halt-mode draws 2.5-3.0microA (32kHz/3V), while sleep-mode current drain is 1.0-1.5microA (3V).

Full-scale production of S1C8E108 chips will start in the summer of 2004. A production volume of 2mn units per month is expected. In future, Epson will consolidate the line-up with models equipped with liquid crystal drivers in order to support liquid crystal display products.

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