Tunnelling boost for SOI
UMC claims a new engineering technique enhances silicon-on-insulator (SOI) transistor performance. The direct-tunneling induced floating-body potential manipulation technique magnifies a key device physics behaviour to provide PMOS transistors with a 30% increase in drive current compared with conventional body-grounded SOI transistors, it is claimed.
Unlike other performance enhancing techniques such as strained silicon or multi-gate transistors, this new technique suffers no additional process complexity, which translates into a better position in terms of manufacturing cost and yield, the company says.
Direct tunneling derives from quantum mechanics where electrons or holes can effectively jump through a thin insulation barrier. This usually undesirable behaviour can be manipulated with simple design layout structures, according to UMC. SOI devices could take advantage of this to circumvent the uncontrollable parasitic floating-body effect. With this extra control, the transistor behaves much more predictably in addition to the performance gain.
With traditional SOI transistors, the body of the device sits on an insulator and is therefore electrically isolated from the rest of the circuit. The isolation leads to the floating body effect, which creates an uncontrollable mode that can make the transistors behave erratically in certain circumstances.
A series of publications discussing this technique have been published in the April and May editions of the IEEE's Electron Device Letters and Transactions on Electron Devices.
