Process development

STMicroelectronics, CEA-Leti and Aixtron have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes. So far, equivalent oxide thickness (EOT) values of 1.15nm or 11.5Angstroms have been achieved based on hafnium dioxide / silicon dioxide / silicon (HfO2/SiO2/Si) stacks offering leakage current densities as low as J(L)=6.8x10(-2)A/cm(2) at 1.5V.

The new process significantly reduces transistor leakage current by the deposition of high-k gate-insulation material. The Advanced Modules team of researchers from ST and CEA-Leti at ST's Crolles facility is using Aixtron's Tricent reactor and Atomic Vapour Deposition (AVD) technology. The HfO2 deposited layer process was developed in conjunction with Aixtron and the wafer processing and the characterisation were performed at CEA-LETI facilities in Grenoble.

UMC claims a significant performance enhancement on 45nm p-channel transistors through substrate engineering. UMC's engineers have implemented a new substrate crystalline orientation scheme to realise a transistor drive current increase of 30%, compared to devices fabricated on silicon substrates with conventional surface orientation. Performance gain is based on the same level of device leakage.

A 70% hole mobility gain was demonstrated, resulting in a 30% increase in PMOS drive current. In addition to the performance gain, the company reports an improved distribution of device parameters, indicating an increased potential for future manufacturability. Moreover, improved noise characteristics make this method suited for analogue applications. Details will be reported at the Symposia on VLSI Technology and Circuits to be held June 15-17, 2004, Hawaii.

The description sounds similar to a technique reported by IBM last year (Bulletin 498, September 12, 2003). In silicon, resistance to carrier flow is direction dependent. The easy current flow directions are different for electrons and holes. By bonding wafers with different crystal orientations and then carrying out etch and deposition steps one can create a substrate with different crystal orientations in different areas. One can therefore build the PMOS and NMOS transistors that make up CMOS with optimal substrate performance for each type. In the past UMC has worked on technology with IBM and Infineon Technologies. More recently, however, it has tended to carry out (at least publicly) it own development work. IBM's relationship has continued with Infineon and has brought in Singapore's Chartered Semiconductor in as foundry partner.

Trikon Technologies reports that a number of DRAM manufacturers are evaluating its patented Flowfill and low-k Flowfill inter-metal dielectric gap-fill technologies for sub-90nm device production. Infineon Technologies recently invested in Trikon's Planar 300 Flowfill system for the deposition of inter-metal dielectrics for DRAM products. According to Trikon, Infineon demonstrated that Flowfill's gap-fill and planarisation capability enabled them to eliminate entire dielectric CMP steps resulting in significant cost reductions. One other DRAM manufacturer has evaluation equipment in-house and others IC producers are performing external assessments.

According to Trikon's director of marketing, David Butler, apart from one notable exception, DRAM makers continue to use the traditional aluminium metallisation along with dielectric gap-fill processes. This, Butler says, is because the performance benefits of copper are not so relevant to the memory sector.

"The factor that limits the available market for us is the size of the trench - Flowfill becomes more compelling as aspect ratio rises," says Butler. "As nodes shrink we expect opportunities for Flowfill to increase as incumbent technologies such as high-density plasma (HDP) or sub-atmospheric chemical vapour depostion (SACVD) start to have problems filling the narrow gaps. The situation now at geometries at or just below 90nm is that Flowfill is gaining some traction for mainly cost reasons, where the degree of planarity we can offer means lower CMP burden compared to the more established competition."

Reverse engineer Chipworks has been analysing Xilinx' XC3S200 Spartan-3 FPGA and finds a discrepancy in the reported 90nm process techniques in terms of the inter-metal dielectric. According to Chipworks, Xilinx publicised their move to 90nm technology over a year ago, stating that the Spartan-3 product would be made in both the IBM and UMC foundries on 300mm wafers. It uses seven layers of copper and one aluminium layer.

Dick James, a senior technology analyst for Chipworks, reports: "We found transistor gate lengths less than 70nm, and a metal 1 (M1) pitch of 250nm. While these do not meet the letter of the ITRS (International Technology Roadmap for Semiconductors) definition of 90nm feature sizes, they are in the range of 90nm processes announced by other companies. For example, Chipworks measured Texas Instruments' M1 pitch as 300nm and gate length as 48nm, and Intel's M1 pitch is 230nm and gate length is 45nm. ITRS sets the dimensions at 214nm and 37nm, respectively."

UMC's different and more conservative approach for the Xilinx chip lies in the dielectric layers used in the interconnect structure. SIMS analysis shows that the intermetal dielectrics (IMDs) are FSG (fluoro-silicate glass), with undoped glass at the top level. The copper metal is dual damascene, and no trench etch-stop layers have been used, therefore minimising the effective k-value of the combined dielectric and metal-cap layers.

James comments that "this is the first part that Chipworks has seen that is claimed to be 90nm and is still using only the FSG that is universal in 130nm processes. Other 90nm technologies from Intel, Texas Instruments and Sony/Toshiba have all used low-k at the critical metal levels. Consequently, the question is - can we classify this as a 90nm part, or is it a shrunk 130nm device?"

UMC's publicity for their 90nm L90 process details the M1 pitch as 240nm, and the gate length as 70nm. The IMD is given as FSG at the upper metal layers, with low-k (k-2.7) at the lower levels. Reported press indicates that UMC is planning to use Novellus' Coral carbon-doped oxide as their low-k material. So the part meets the published dimensions for 90nm, but not the structural details.

Chipworks comments that from Xilinx' perspective, UMC has presumably met the performance specifications for the XC3S200 - the sample is a standard speed product. The major advantage from 90nm processing is the die size reduction giving more than twice as many die per wafer, compared with the equivalent product in 130nm technology.

The Spartan product is Xilinx' low-cost FPGA series, where the emphasis is on the performance/price ratio, targeted at the widest range of consumer applications. Xilinx is using the 90nm technology to drive their target pricing down to less than $12 for a 1mn-gate device and $2.95 for a 50,000 gate FPGA (about 17,000 and 1700 logic cells respectively).

UMC reported its 90nm progress with customers. First working 90nm customer silicon came in March 2003. Since then, the process has been qualified for volume production by several major customers, including Xilinx and Texas Instruments.

In the coming months, UMC expects to expand 90nm production on 300mm wafers at its Fab 12A facility in Taiwan, based upon current customer requests. The technology is also due to be brought to volume production at UMCi, the 300mm foundry subsidiary located in Singapore. The development of 65nm and 45nm technologies is already underway.