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News Article

Packaging

ST Assembly Test Services (STATS) has developed a "Chip Scale Module Package" (CSMP) thin-film technology, which involves the fabrication of passive devices such as resistors, capacitors, inductors, filters, baluns and interconnects directly onto a silicon substrate.

ST Assembly Test Services (STATS) has developed a "Chip Scale Module Package" (CSMP) thin-film technology, which involves the fabrication of passive devices such as resistors, capacitors, inductors, filters, baluns and interconnects directly onto a silicon substrate. CSMP enables analogue and digital functions to be independently optimised and combined for a distinct performance and cost advantage over system-on-chip implementations.

STATS will offer the CSMP technology as a full turnkey service, providing fully characterised design libraries of resistors, capacitors, inductors, filters, and baluns. The design library will include electrical models delivered as touchstone files for engineers using linear frequency-domain simulators or equivalent electrical models for non-linear and time-domain simulators. Initial parts libraries cover the dc-6.0GHz frequencies, with filters and baluns designed for the 2.45 and 5.6GHz 802.11 bands, addressing WLAN, cellular handset, Bluetooth and other wireless markets.

STATS has qualified two package versions: CSMP-stPBGA, which is wire bonded onto a small thin plastic ball grid array (stPBGA) platform, and a flip chip solution mounted onto a land grid array (LGA) platform. Other package family extensions such as quad leadless package (also referred to in the industry as flat-pack, no lead) and quad flat pack (QFP) are planned. Unitive has developed a process to apply a new spun-on polymer coating technology that permits further reductions in the size of integrated circuits while promising improved performance and dramatic increases in wafer-level chip-scale packaging (WLCSP) reliability.

A typical single-layer polyimide coating is often used as a stress buffer for wire bond, flip chip and ball load packaging solutions. However, Unitive's process can stack the polyimide layers and integrate the material with thick-plated copper. The company sees market application for wireless phones, PDAs and other portable devices. The electronic subsystems enabling this performance must be integrated with ever increasing functionality, perform with greater reliability and in the same or smaller space.

Last month, Unitive opened a new die level processing (DLP) facility in the USA. Integrated services include design, wafer bumping, multi-layer redistribution, backgrind, dicing, probe, tape and reel, backside laminate, backside metallisation and laser marking. The company has also developed and qualified an electroplated lead-free SnAg wafer bumping technology. Last year Unitive introduced a 300mm electroplated wafer bumping production line at its Hsinchu, Taiwan, manufacturing facility.

Fabless IC supplier Enpirion has integrated an inductor into its Power System on a Chip (PSoC) synchronous buck converter. The EN5330 is the first of the company's iPOWER line of integrated DC-to-DC converters for use in Point of Load (POL) applications including servers, personal computers, laser printers, set-top boxes, telecoms and data networks.

The company claims that its EN5330 reduces real-estate requirements and part count by more than half. The patented approach enables a 10x switching-frequency improvement, integrating a PWM controller, output FETs and magnetic components into a single turnkey IC package with a standard TSSOP footprint, Enpirion claims.

The EN5330 in a dual flat no-lead (DFN) TSSOP footprint package covers just over 100mm2 of board space. Including the minimum of three external components, the entire DC-to-DC converter can be placed in as little as 135mm2 of single-sided or 102mm2 of double-sided board space. The height profile is 2.2mm and efficiencies up to 90% are claimed.

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