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The Power Of Design

One of the biggest challenges at the 90nm node is power dissipation, which causes chips to heat up and drains batteries. World number one foundry TSMC believes that electronic design automation will play a key role in overcoming this tricky problem.

One of the biggest challenges at the 90nm node is power dissipation, which causes chips to heat up and drains batteries. World number one foundry TSMC believes that electronic design automation will play a key role in overcoming this tricky problem.


Any visitor to Europes major trade shows this year knows that multimedia convergence is at last beginning to mean something for consumers. At the GSM World Congress in Cannes or CeBIT in Hanover, optimism had returned and hype was on the sidelines.
Consumers are close to enjoying multimedia digital technology in the home and in the hand. The arrival of 3G and the mass penetration of broadband in the last 12 months reinforce the perennial challenges for the electronics sector: meeting demands for greater functionality and lower battery consumption.

The semiconductor industry has responded to the challenges, particularly with the migration to advanced geometries. The recent move to 90nm represents the most significant geo-metry step of the last decade. However, as the industry gets used to volume production at the 90nm node, design trade offs are weighted heavily in favour of power management.

The path to 90nm was cleared through the process of developing the earlier, 0.18-micron and 0.13-micron technologies. These process geometries are today the most widely used technologies in the foundry industry.

As the 0.13-micron process is mature and highly stable, yields at this node are the highest that can be expected. This means the process can be reliably used in products as diverse as programmable logic and communications infrastructure devices, cell phones and graphics processors as well as DVD players and network processors.

To ensure maximum design flexibility, the 0.13-micron complementary metal-oxide semiconductor (CMOS) logic process includes general purpose, high-speed and low-power options, all with multi-volt capabilities. The offerings comprise logic-based and true mixed-signal processes, high-density memory and a wide variety of process-proven libraries and intellectual property (IP) elements.

To reduce RC delay for improved performance, all-copper interconnect and low-k intermetal dielectrics for 0.13-micron technology and beyond are available. These include both fluorinated silicon-glass (FSG) and low-k based intermetal dielec-trics.

TSMC is the only company using low-k dielectrics at the 0.13-micron node. The 0.13-micron technology employs eight metal layers and has a poly gate length as small as 0.08µm. On the strength of TSMCs 0.13-micron rollout, all of the foundrys 90nm processes use copper and low-k dielectrics.

The move to 90nm
The migration to the next geometry node has now taken place and the market for mass-producing 90nm technology is ripe, given the strong growth in consumer 3G and digital media products, among others.

TSMCs dedicated 90nm technology, called Nexsys, is the foundry industrys first true volume 90nm process and moved to volume production in the fourth quarter of 2004. The process technology delivers a two-times gate density improvement, 35% faster speed as well as a 60% improvement in active power savings compared to the 0.13-micron process.

Trade offs at sub-micron
Despite the recent advances in 90nm production, there are challenges that must be addressed. For instance, there has been some industry concern that, with up to hundreds of millions of transistors available on a 90nm device, the sheer complexity of the design cannot be satisfied by traditional electronic design automation (EDA) tools.

Likewise, while Moores Law increases transistor density by over 50% per year, designer productivity levels simply cannot keep up. The emerging system-on-chip (SoC) market demands silicon-tuned EDA tools, silicon-validated and reusable intellectual property, and vast amounts of on-chip memory, indicating that demand for the newest technologies continues unabated.

TSMC has attempted to address some of these challenges with its Nexsys process. The Nexsys 90nm process is a full SoC platform that provides both CMOS logic and mixed-signal options with embedded high-density memories including 1TRAM (Transimpedance amplifier), 6TRAM, 8TRAM and Flash technology.

The Nexsys 90nm logic family includes the high-volume "G" process as well as low power and high-speed options. Each supports multiple voltage options, including low, standard and high, in a single design. Operating voltage is 1V to 1.2V; the IO voltages range from 1.8V to 3.3V, depending on family member. And SRAM memory densities range from 1.65-micron to 0.99-micron.

The technology also features the most extensive portfolio of silicon-proven IP and libraries as well as a complete EDA environment with dual implementation flows using tools from leading EDA vendors.

Power dissipation
At nanometre process geometries, power leakage is a key concern. As feature sizes of CMOS transistors are scaled down to increase circuit performance and packing density, interconnect (RC) delay and cross-talk are increased by coupling capacitance.

Moores Law remains valid only because RC delay is negligible vis-à-vis signal propagation delay. But for sub-micron technology, this is no longer true and RC delay dominates.

Likewise, the proximity of interconnect lines with the shrinkage of features results in more cross-talk between interconnect lines, a phenomenon that was not a concern at larger process geometries. It is for these reasons that advances such as multi-volt transistors, low-k dielectrics and proven design for manufacturing (DFM) rules offer advantages.

To address power leakage, the Nexsys process features multiple transistor types for optimised power/speed/leakage trade offs.

This is achieved by a triple gate oxide option that facilitates three different oxide thicknesses on a single chip.

The triple gate oxide feature removes design restrictions caused by various core/IO combination requirements. The transistors can be isolated and turned on and off with no discernible increase in chip size.

The process also features low-k dielectrics of 2.9 or lower and up to ten layers of dual-damascene copper metallisation. With a linear shrinkage of 70% to 75% compared to the 0.13-micron technology, the 90nm technology is poised to become the de facto SoC process technology platform standard.

The Nexsys process is also backed by TSMCs Reference Flow 5.0. As the first reference flow to provide critical power closure and to integrate chip-to-package design for nanometre SoC integrated circuits, TSMC Reference Flow 5.0 builds on a dual-track methodology, which was constructed with the help of major EDA developers Cadence Design Systems and Synopsys.

The fifth-generation flow features some important enhancements compared to the previous version, including new design-for-test, design-for-manufacturing and flip-chip design capabilities. But none is more essential than power closure, an increasingly problematic element of IC design.

To achieve power closure and forestall leakage, a number of advances have been required in dynamic power optimisation, IR final verification, multi-volt libraries and dynamic IR-drop methodology. For instance, dynamic power optimisation requires level shift cells and isolation cells to allow blocks of circuits to run at different voltages and prevent circuit leakage between power domains.

Reference Flow 5.0 provides designers with an automated insertion methodology, control schemes and power connection methods for implementing level shift cells and isolation cells. This avoids altogether the task of manually inserting hundreds or even thousands of these elements.

Similarly, in addition to the multi-vt flow introduced in TSMC Reference Flow 4.0, which enables designers to take advantage of the multi-vt libraries in TSMCs 90nm Nexsys technology, the new reference flow introduces a substrate bias implementation flow with timing impact silicon data as a new route that the designers can resort to to further reduce chip leakage.

Other features of Reference Flow 5.0 enhance the ability to view power management in a more realistic way. For instance, in the past, static IR drop analysis was the key method for analysing system power issues.

However, such a capability provides a simplified analysis that is based only on the pure resistive network and average power over the design. As such, it is not adequate for systems with millions of transistors and dynamic events that may cause much worse IR drop effects.

A key element of the Reference Flow 5.0 solution is to create a dynamic IR-drop methodology that addresses power integrity across the range of operational states and including not just the core, but also the IO and package design. The challenge for many fabless companies today is that they often lack the necessary expertise and manpower to execute 90nm designs in a short time. There is therefore an increasing need for close interaction between chip designers, EDA companies, IP providers and foundries. This will help to make adoption of 90nm technology by the fabless industry pain free and speedy.

In order to maintain the technological progress required to address the trade offs associated with smaller geometries, it is clear that the industry will increasingly have to rely on the fabless model, as foundries and the EDA partners lead the drive for advanced innovation.












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