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Progress in miniaturising electronic components for portable devices such as mobile phones and MP3 players is being boosted by the development of ultra-thin packaging techniques. Luu Nguyen and Sadanand Patil of National Semiconductor report.

Progress in miniaturising electronic components for portable devices such as mobile phones and MP3 players is being boosted by the development of ultra-thin packaging techniques. Luu Nguyen and Sadanand Patil of National Semiconductor report.


Mobile phones remain the major driver for semi-conductor volumes, with well over 500 million handsets shipped in 2004. The integration of cameras in cell phones has accounted for the sharp increase in sales, with newer high-end models incorporating two colour displays. Customers desire for more features and applications to be packed into the phones has fuelled advanced semiconductor packaging development, including many chip scale packages (CSPs) with single and stacked dies. Aside from the higher functionality, key requirements of portable applications are small form factor, light weight and high reliability.

National Semiconductor introduced early last summer the industrys first family of 0.4mm ultra-thin packages in micro SMDs (wafer level-CSPs) and LLP (leadless leadframe packages) to allow original equipment manufacturers to build thinner portable devices, smaller phones, lighter displays, loaded MP3 players and more versatile PDAs.

This article will focus only on the LLP and the challenges encountered in developing these packages. These CSPs are among the most inexpensive and versatile packages in the industry, since they are typically wirebonded and take advantage of the mature leadframe industry and existing infrastructure. No solder balls are attached to the packages.


According to market analyst TechSearch International, a 30% yearly growth in leadframe-based CSPs is anticipated over the next few years. These packages are also known in the industry as dual flat no-leads (DFNs) and quad flat no-leads (QFNs), depending on whether bond pads are on two or four sides of the package.

As the leadframe is on the bottom of the package, superior thermal performance can be obtained compared to a leaded package of similar size and pin count. The die attach pad can be soldered directly to the board, resulting in a typical ØJA about half of the leaded counterparts. For instance, a 48-L, 7x7mm LLP operating at an ambient environment of 700C can dissipate up to 2.5W, compared to only 1.5W for an equivalent TQFP. Furthermore, since the package is totally encapsulated by the mould compound except for the pads, the ensuing low parasitics favour RF applications.

There are currently two package outline versions of the LLP registered with the JEDEC JC-11 sub-committee: MO-220 with leads on four sides; and MO-229 with leads on two sides. The LLP package has seen its thickness steadily shaved from 0.8mm at its introduction in early-2001 to 0.6mm a year later, to 0.4mm today. This thickness reduction path was achieved through advances in a number of enabling technologies such as thin wafer backgrinding and handling, leadframe design and manufacturing, low loop wirebonding, low stress moulding and high density strip testing. In addition, the ultra-thin LLP packages meet the Moisture Sensitivity Level (MSL) 1 at lead-free reflow temperature (2600C).

How was the package constructed? Table 1 compares the key attributes between the standard 0.8mm-thick package and the ultra-thin 0.4mm version. The slim profile (Figure 1) was achieved using a half-etched leadframe combined with dies thinned down to 75 micron and wirebond loop heights of 125 micron (5 mils).

An extensive evaluation of a combination of backgrinding and wafer polishing was carried out to study characteristics such as wafer thickness uniformity, bow, warpage, impact stress and indentation fracture strength for a range of thickness values (200, 100, 75 and 50 micron) using backgrinding and polishing equipment from different suppliers.

Breakage of the thinned wafers during handling was a yield concern. Variation in the fracture stress depended on the post-grinding stress relief method (eg chemical etch, mechanical polish, plasma etch or dry polish), with chemical etching providing the most cost-effective high etch rate performance.

Testing highlighted a number of issues related to die strength, loop height and MSL performance. For instance, the tests indicated that the die fracture strength was affected by chippage and the quality of the sawing operation. High die strength enhances assembly throughput and packaging reliability.

Cracking was detected for 50 micron-thick dies during high speed pick and place for die attach, while no damage was observed for 75 to 100 micron-thick dies. Similarly, using 25 micron (1 mil) gold wire, necking of the first bond was observed for standard loops under 4 mils high, leading to weakened wire pull and ball shear strength. Furthermore, the MSL assessment also showed some delamination at the die/die attach interface for 50 micron die assembled and tested during autoclave.

The major constraint imposed during this evaluation dictated that the assembly flow for the ultra-thin LLP should not deviate from the standard LLP flow in terms of equipment usage, yield and throughput. For instance, 50 micron-thick dies could be used for even thinner packages, albeit at a lower yield due to potential saw damage and lower die attach throughput.

Other sub-100-micron-high bond loops could also have been used, since some wirebonding equipment suppliers have recently introduced new low loop-enabling software. However, these modules were still in beta evaluation mode, and all had somewhat slower speed compared to the standard process. Along the same line, a new material set (eg mould compound and die attach) could also be introduced to provide better die coverage, good fillet height control, improved mouldability and enhanced MSL performance of the packaged 50 micron-thick dies. However, this would have led to non-standardised materials for the same package families, and ultimately to higher inventory cost.

The extensive evaluation showed that some trade-offs needed to be considered to obtain an optimised process for the ultra-thin LLP. The half-etch leadframe design selection relaxed constraints in die thickness and wirebonding loop heights. Die breakage during pick and place and die attach operations were eliminated when 75 micron dies were used.

Similarly, wirebonding could be performed at high Cpk without switching to a different wire type, or adopting a slower software module for low loop profile. Using the same material set also alleviated concerns about mouldability in narrow gap mould cavities, wire sweep and voiding, while also allowing optimisation of the MSL performance for 260oC lead-free board assembly. For the end customers, board assembly of these ultra-thin packages is no different from handling of their standard counterparts. No new equipment is required.

Should there be a need to rework a package, the same guidelines for replacing a standard LLP are applicable.

Extensive board level reliability was also conducted to ensure that these ultra-thin packages satisfy the exacting requirements imposed by portable applications. Thermal cycling, drop, vibration and flex testing were performed along with standard counterparts for control. The ultra-thin packages exhibited the same level of reliability performance as their thicker counterparts.

Figure 2 depicts different views of a 10-L ultra-thin LLP. The exposed die attach pad and leads are shown in (a) with a lead-free plated finish of matte tin. The top view (b) is seen with the laser marking. Mould compound was removed in (c) to display the die layout and low loop wirebonds.

It is clear that the thickness reduction migration path is far from over. As process windows are better refined for the packaging enabling technologies, and demand for ever smaller form factor becomes insatiable, we can expect even thinner packages and variations of ultra-thin packages to emerge in future portable applications.










Fig1

 









Figure2a

 









Figure2b

 









Figure2c



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