Info
Info
News Article

Copper-bottomed Metrology

Metrology is becoming an ever more challenging area as a result of smaller feature sizes, copper interconnects and new fragile low-k materials that are susceptible to damage during measuring. Philips AMS take a look at how these challenges are being met.

Metrology is becoming an ever more challenging area as a result of smaller feature sizes, copper interconnects and new fragile low-k materials that are susceptible to damage during measuring. Philips AMS take a look at how these challenges are being met.


Year after year, the semiconductor industry has created chip designs with higher circuit density and faster performance. The traditional approach to scaling the chip was to reduce all dimensions while basically relying on the same materials: SiO2 for the gate dielectric at the transistor level, aluminium and SiO2 as the conductor and insulator at the interconnect levels. Chip speed was dominated by effects at the transistor level, rather than by the interconnects. But this run came to an end when the interconnect delay became a significant factor in circuit speed. Switching to copper wiring, with lower electrical resistance than aluminium, gives a significant boost to interconnect performance. Copper was first introduced in leading-edge chips in 1998, and is rapidly being adopted by all major manufacturers for high-end products. To further boost performance, the traditional interconnect insulator of SiO2 is being replaced by a progression of low-k dielectric materials yielding lower capacitance, allowing tighter spacing of wires. The copper and dielectric materials are layered in a complex stack with an increasing number of layers (Figure 1 - left).

Fabrication of copper interconnects is very different from aluminium, and requires different equipment and processes. Aluminium is patterned with a subtractive method, in which the metal films are deposited as a blanket across the wafer, then patterned and etched, with subsequent deposition of insulating dielectric to fill the gaps between the etched metal lines. However, no practical etching techniques are known for copper. Therefore, copper interconnects are fabricated with a Damascene process, in which the copper is embedded in trenches etched into the dielectric (Figure 1 - right). First the dielectric layer is deposited and then etched to create a pattern. Next a barrier metal and overlying copper seed layer are deposited across the wafer, using physical vapour deposition (PVD). The barrier metal, typically Ta-based, prevents copper diffusion into the insulator and silicon, and also provides an adhesion layer for the copper seed. Copper electrochemical deposition (ECD) is then used to complete the filling of the etched pattern. Finally, the wafer is polished with chemical-mechanical planarisation (CMP) to remove the copper overburden. The introduction of any new materials and equipment into a manufacturing process is generally problematic. However, beyond the newness factor, there are several issues that make it inherently more difficult to control film thickness uniformity in a copper process than in an aluminium one. These include:

l Pattern-specific behaviour In an aluminium process, the metal is first deposited across the wafer and then etched and patterned. As a result, the uniformity of the metal thickness across the wafer does not depend on the details of the pattern. However for copper, the film thickness may depend greatly on the local details of the die pattern. CMP performance, for example, varies with feature type due to the variability of dishing and erosion (Figure 2). As a result, metrology must be performed on patterned wafers to get an accurate picture of the film thickness results.

l Interactions between process steps Fabrication of copper interconnects requires three different metal process steps in sequence in three different tools. Non uniformity in the deposition of the copper seed layer will affect the uniformity of the electroplating. Similarly, non-uniformity of the electroplating will affect the uniformity of CMP. Integrating all three processes creates an extra challenge.

l Wafer-to-wafer process variations In copper CMP, the state of the process tool changes slightly for almost every wafer polished, due to the gradual degradation of the polishing pad and slurry and the fact that the polishing pad must constantly be reconditioned. Similarly, the ECD step may show variability due to gradual changes in the electroplating bath.

l Its not just copper It is important to remember that there is more to the copper process than just copper. A copper interconnect process includes other materials, which add their own production and metrology challenges. These include tungsten (plugs used to link the transistor to the copper interconnect - see Figure 1), barrier metals (typically Ta or TaN, used to encapsulate the copper in the dielectric trenches) and low-k dielectrics (to reduce the electrical resistance of the interconnect).

Given the above challenges, the engineers implementing a copper/low-k interconnect architecture have a number of film metrology issues to worry about in process development and production, including:

* Low-k material properties Selecting and characterising a low-k material with adequate mechanical strength and other properties, and monitoring the material in production.
l Metal film deposition uniformity Keeping each of the metal deposition steps uniform, dealing with interactions between barrier/seed and electroplating, and dealing with the pattern-specific effects of electroplating.

* Fill voiding Ensuring that the electroplating uniformly fills the trenches, without leaving voids.

* Copper resistivity Monitoring the electroplating process to make sure that processing conditions, including additive concentration and annealing, produce a film with desirable electrical properties.

* CMP parameter optimisation Choosing the right combination of CMP tool parameters to optimise performance for the specific pattern layout to be processed.

* Dishing and erosion Minimising metal loss in wide areas (dishing) and arrays (erosion) during copper CMP.

* Residual metal Ensuring that no copper or tantalum remains after CMP, which would short the circuit or cause reliability problems.

These issues all create a strong demand for new film metrology techniques.

The advent of the copper and copper/low-k era creates not only additional demands for film metrology, but demands for new kinds of film metrology that were not needed for aluminum/SiO2 processes (Table 1). For an aluminium process it was sufficient to measure metal film thickness with a four-point probe on blanket monitor wafers, because the deposition uniformity was not pattern-specific. Dielectric film metrology of the interconnect structure consisted primarily of oxide thickness measurement with transparent film tools such as reflectometers or ellipsometers.

While on-product measurement of metal film was not a requirement for aluminium processes, laser-sonar techniques providing this capability were nonetheless introduced for aluminium production in the late-1990s. This provided additional capability, at additional cost, that could in principle be used to reduce monitor wafer consumption. For copper production, however, on-product measurement becomes not just a cost-saving tool but also a metrology requirement, due to the pattern-specific nature of copper processing.

Laser-sonar was initially adapted from aluminium applications to copper to meet these new needs. However, process engineers have struggled with applying the method to copper. While laser-sonar does measure metal in field areas on patterned wafers, using it to measure patterned structures such as arrays of lines and vias - the features for which copper processing is particularly unique - has been and remains a difficult challenge. Additionally, the technique struggles with copper on low-k films.

In the dielectric area, transparent film optical measurements such as reflectometry and ellipsometry have been successfully adapted to measure low-k film thickness. However, there are also new metrology requirements for low-k films, such as characterisation of film stiffness and other properties, which are not addressed by these metrologies and for which non-contact, non-destructive measurement techniques are desired.

Philips Advanced Metrology Systems (AMS) has developed a new metrology technique - SurfaceWave - that solves many of these problems.

The basics of the SurfaceWave technology are simple (Figure 3). Laser excitation is used to create an acoustic wave that travels along the surface of a sample film. A probe laser detects the passing wave. Computer analysis of the wave speed and other characteristics of the signal waveform are used to determine film thickness or other sample properties. The main principle is that the presence of a film on a substrate will change the speed of an acoustic wave travelling along the sample surface.

Since the detector is off the axis of the reflected probe beam, the detector does not register any signal until the acoustic wave is created, so the measurement is done against a dark background, yielding a high signal-to-noise ratio. A short pulse of laser light (532nm) is used to excite an acoustic wave of fixed wavelength using a striped pattern, and this wave travels laterally in the film. The probe laser light (830nm) diffracts off the passing wave, and the detector registers the diffracted signal intensity versus time.

A typical signal waveform is shown in Figure 4, with the waveforms frequency spectrum shown in the inset. Analysis of the frequency spectrum is used to determine wave speed and to calculate film thickness.

While the basics of the technique are simple, the waveforms contain a rich set of information. Analysis of secondary characteristics, such as decay rates and other features, can be used to determine more information about the film stack.

As an in-fab metrology technique, SurfaceWave has several important advantages. The system uses compact solid-state lasers and is vibration-tolerant, making it highly robust. In addition, the high signal-to-noise ratio of the technique means measurement is fast, with typical data acquisition times of ~1 second per site. SurfaceWave was specifically developed for copper film metrology. It provides the ability to measure not only metal field areas of product wafers, but also arrays of finely patterned features such as lines and vias. This allows it to be applied to pattern-specific process development issues arising from metal deposition and CMP. It is able to measure both copper and its associated metals (tungsten, tantalum, tantalum nitride) on both SiO2 and low-k dielectrics. And it provides the capability to measure dielectric thickness or properties such as film stiffness. The application range of SurfaceWave is illustrated in Figure 5, showing the capabilities the method provides at each film processing step of the interconnect fabrication cycle.

Process engineers need metrology tools at both the early and late stages of their work. During the early stage, development and pilot process implementation, metrology is needed to allow rapid character-isation of film process issues. Here the speed and small spot size of the SurfaceWave measure-ment are beneficial. Because SurfaceWave can measure sites very quickly, it enables full-wafer mapping capability that gives the engineer additional perspective on the process issues. This is particularly true for copper development, where pattern-specific effects of ECD and CMP require repeated studies on test patterns to determine optimum process parameters. In the late stage of development, when a process is entering pilot or full production, metrology is equally important to monitor film process equipment and ensure stability of the results. Here repeatability, ease-of-use, and throughput - as provided by SurfaceWave - are the most important factors.

As the semiconductor industry matures, there is an increasing desire to employ metrology not only for trouble-shooting or conventional process control requiring human intervention, but also for advanced process control (APC) - real-time feedback and feedforward of metrology data for automated adjustment of process equipment. This promises to reduce manufacturing cost by keeping process tools in better control.

The logical extension of APC is to include metrology systems integrated directly into a process tool, where the metrology can be used to monitor a high fraction of the processed wafers without significantly reducing overall throughput or increasing footprint.

In order for APC and integrated metrology to succeed in a particular application, the metrology tool must be robust, highly repeatable, and compact. Philips AMSs SurfaceWave technology has been designed to be integrated into metal film processing tools, thus meeting this need.










Fig 1

 









Fig 2

 









Fig 3

 









Fig 4

 









Fig 5

 









Table 1



AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS
DISCO's Completion Of New Building At Nagano Works Chino Plant
New Plant To Manufacture Graphene Electronics
Changes In The Management Board Of 3D-Micromac AG
Obducat Receives Order For Fully Automated Resist Processing Tool From A Customer In Asia
EV Group Establishes State-of-the-art Customer Training Facility
Tower Semiconductor Announced Program Creating An Integrated-Laser-on-Silicon Photonics Foundry Process
Imec Demonstrates 20nm Pitch Line/Space Resist Imaging With High-NA EUV Interference Lithography
AP&S Expands Management At Beginning Of 2021
ITRI And DuPont Inaugurate Semiconductor Materials Lab
SUSS MicroTec Opens New Production Facility In Taiwan
Panasonic Microelectronics Web Seminar
South Korean Point Engineering Chooses ClassOne’s Solstice S8 For Advanced Semiconductor Plating
Tescan And 3D-Micromac Collaborate To Increase The Efficiency Of Failure Analysis Workflows
K-Space Offers A New Accessory For Their In Situ Metrology Tools
Onto Innovation Announces New Inspection Platform
U.S. Department Of Defense Partners With GLOBALFOUNDRIES To Manufacture Secure Chips At Fab 8
TEL Introduces Episode UL As The Next Generation Etch Platform
Belgian Initiative For AI Lung Scan Analysis In Fight Against COVID-19 Goes European
Siemens And ASE Enable Next-generation High Density Advanced Package Designs
Will Future Soldiers Be Made Of Semiconductor?
ASML Reports €14.0 Billion Net Sales
GOODFELLOW Confirms Membership In The BSI UK Graphene Group
Cadence Announces $5M Endowment To Advance Research
Can New Advances In CMOS Replace SCMOS Sensors In Biomedical Applications?

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification} Array
Live Event