CEA Leti announces low power transistors for 45nm and beyond
Just one year after the inauguration of the Nanotec 300 research platform for the 45 and 32 nanometer microelectronics nodes, CEA Leti announced the successful completion of its first High K metal gate transistors on 300mm wafers.
The first wafers have been produced in cooperation with the Crolles2 Alliance of STMicroelectronics, Freescale Semiconductors and Philips Semiconductors. CEA Leti has shown that it is possible to integrate high permittivity insulators (HfSiON) and metal gates into advanced MOS structures on 300mm wafers, thus drastically reducing parasitic leakage current and avoiding gate depletion. Circuits produced with this breakthrough technology combine very low off-state power consumption with high performance and speed. The new gate stack withstands thermal treatments of 1000 degrees C-10sec, and is hence fully compatible with standard planar CMOS architectures. This opens the pathway to 45 nm technologies targeting portability and performance.
