The Third Dimension
3D system-on-chips could provide semiconductor makers with an easy method of combining the benefits of both system-in-package and system-on-chip, writes Ziptronix vice president Bill Knapp.
Ask chip designers today about the challenges facing them in ASIC or system-on-chip (SoC) design and they will likely break out a laundry list of concerns, obstacles, tradeoffs and pitfalls that make it difficult for this chip segment to keep pace with Moores Law. Yet, as 65nm design rules loom on the horizon, designers continue to look for ways to overcome some of their most persistent and vexing challenges. Challenges such as transistor leakage, parasitics and ever-increasing power and memory requirements justify their quest for new practices that will enable greater functional integration per a given area of silicon. Memory integration is one of the roadblocks that prevent ASICs and SoCs from truly scaling in line with Moores Law. A further examination of this problem suggests a need for a new methodology that can deliver better device cost, size and performance.
Nearly 80% of the total area of todays leading edge SoCs and ASICs can be consumed by memory. Density of embedded memory in a logic-based process is inefficient but the ever-increasing need for better performance and higher complexity demands increased memory integration. This constraint forces chip designers to develop devices with large die sizes that are costly and inefficient. Since the density and performance of embedded system memory is an order of magnitude less than what is available with off-the-shelf memory device technology, device sizes in SoCs are growing disproportionately.
This results in higher unit costs that make SoCs increasingly impractical for many consumer electronics categories. However, if the integration of memory into a SoC could be achieved at a density comparable to off-the-shelf memory devices, then unit cost and die size concerns would begin to dissipate. The solution may be found in the use of three-dimensional system-on-chip methodology (3D SoC), which makes it possible to integrate highdensity, off-the-shelf memory with logic and processors. Such a methodology will lead to smaller die sizes while delivering high performance.
Using vertical integration inherent in 3D SoCs, it is possible to substantially decrease parasitics, since going through a device (up/down) is measured in microns, whereas vertical interconnects used in the standard SoC approach are measured in millimetres. Vertical integration with high density interconnects makes it possible to terminate more connections at core voltages, further reducing the power requirements proportionally with squared voltage.
A two billion-plus transistor 3D SoC offers physical proof that this methodology delivers the best cost per function, and the greatest amount of functionality in the smallest footprint, as compared to the competing packaging, chip-stacking or alternative chip technologies now available. An outline of how such a chip can be integrated vertically will be explained further.
Understanding the benefits of 3D SoC starts at the chip design level. One of the best ways to demonstrate this is to explore how one 3D SoC was architected and built using readily available, off-the-shelf dice, common semiconductor processes and equipment. The idea is to demonstrate that the technology is real so chip designers will start thinking about partitioning their devices vertically using different technologies that avoid the daunting obstacles found in traditional VLSI integration. Three-dimensional architectures completely change the cost-size-performance equation for silicon devices and will enable chip designers to meet many, if not all, of their original design goals with a minimum of design tradeoffs.
With minor modifications, existing software tools for chip design are 3D compatible. A chip is a 3D device made of one layer of transistors and multiple levels of metal. The tools need to be adapted to handle multiple layers of transistors, functional partitioning and parasitic extraction between levels as well as within a single level of a 3D SoC. Compilation will also need to be modified to compile functions at the die-scale level as well as the transistor level. Ziptronix has seen willingness among tool vendors to create the tool sets to ensure that 3D SoC has the infrastructure in place to make this technology mainstream.
The most popular forms of integrating more functionality into a small footprint are system-onchip (SoC) and system-in-package (SiP). While these methodologies have evolved considerably since their inception, 3D SoC brings together the best of both technologies into a single silicon device. 3D SoC combines the technology diversity of SiP with the performance, cost and integration benefits of SoC to make possible the integration of billion-plus transistor systems on a chip today.
The first step in the process of architecting a 3D SoC is deciding what functionality is needed. The next step entails partitioning the device into diescale functional blocks of memory (DRAM, SRAM, Flash), processors, logic (FPGA, CPLD, etc), ASICs or SoCs. The example explained below will look at integrating commercially available SDRAM, Flash, CPLD and a microprocessor.
Generally, the first level of the 3D SoC uses the most replicated function in the system, which is typically memory. The base level of the device explored here will consist of SDRAM but the flexibility of 3D SoC does not mandate this approach. The size of the first level determines the size of the 3D SoC and is limited only by the final package, die-size and pin-out requirements. To date, we have seen multiple memory die or flash memory die on the first level.
Having dedicated the first level to data memory, the decision now is to determine how many more levels are required for the rest of the system. Today, two levels are supported and we expect it to evolve to three or more levels in the near future. For now, the second level is usually given over to a variety of diverse die-scale functions such as programmable logic, non-volatile memory and microprocessors. All of the dice are market-proven designs with high yields fabricated in optimal processes. For example, the SDRAM is built in a process that optimizes trench capacitors and the microprocessor is made in a logic-optimised process.
Building in 3D
The first level of the device will consist of six SDRAM dice, and the second level will consist of a microprocessor and two flash memory dice.
The memory and processor wafers are first treated with a proprietary bonding process that will enable the die to be placed in different levels using a technique called die-to-wafer bonding (DWB). DWB forms a covalent bond at room temperature in an adhesive-free environment. This is a departure from alternative bonding techniques that use adhesives and heat that can impede device performance, cause thermal degradation or permanently damage properties of the semiconductor device. DWB is undertaken using standard semiconductor practices, chemicals and equipment. In order to make connections between and within the two levels of the device, a multi-level metal redistribution layer (RDL) is deposited between levels one and two and makes all of the connections. Connections can either be made by going through or over the edge of the silicon die, depending on the available circuit-free space or exclusion areas in the die.
The second level of the 3D SoC is added using a standard pick-and-place machine. The pick-andplace machine selects known good die from the flash and microprocessor pre-treated wafers. It then places them in the designated target areas identified on the first level wafer. As soon as the pre-treated dice are placed on the first level wafer, covalent bonds are formed that permanently attach the second level to the first level forming a single multilevel semiconductor device.
Now with the second level in place, connections need to be made from within and below to the first level. These connections are made in two ways: either through the die using through-silicon vias or over the edge using metal vias.
At this point, the multiple, individual dice have become a double-thick multi-level device that is completely interconnected. Now the device is thinned to fit into the final package (300 microns) using a conventional chemical mechanical polish process. Typically, a die can be thinned to 20 microns without impacting its performance.
A third and fourth level can be placed on top of the second level using the same process as above. After the final level is applied, the I/O pads (area or perimeter) are brought to the top level for bump or wire-bond attachment. The 3D wafer is now ready for assembly and packaging.
A 3D SoC device with a similar architecture to the example above was implemented with 1.5Gb SDRAM, 128Mb Flash, and one multimedia microprocessor with reconfigurable logic into a 15mm x 17mm two-level device.
Although it is possible to bond more than two levels of semiconductors, the industry is at the stage now where two-level 3D SoC could potentially be adopted. The first applications have been successful in integrating memory with programmable logic, microprocessors or a traditional SoC. These configurations provide the least expensive form of memory integration at a greater density, bringing considerable cost and performance benefits. However, the infrastructure for building such devices is still evolving in order to make this alternative approach mainstream.
The next steps are the integration of three and four levels of active transistors as well as ASICs and SoCs. This integration can be achieved by employing through-die vias. It should also be noted this methodology is compatible with silicon-on-insulator technology. It will also be possible to create 3D SoCs that incorporate RF and other analogue functionality after digital integration of ICs becomes more refined and mainstream. These RF and analogue strategies may be possible in 3D before they are generally available in mainstream foundry-based CMOS process flows.
More than a package
Today, system-in-package is a mature technology that continues to grow in the market due to its ability to provide a compact, PCB-based solution with a fast time-to-market of two-three months. In this approach, packaged devices are assembled on a small printed circuit board. SiP combines different devices at the package level to provide a compact encapsulated solution that typically consists of twoto-four packages.
Like SiP, the 3D SoC brings together different technologies but at a much smaller footprint than the SiP solution. It also differs in the form of the final solution; where an SiP solution is an encapsulated small printed circuit board with multiple packages, the 3D SoC is a single, multi-level silicon die available in the package of choice. The 3D SoC also provides at least twice the level of integration and up to a five-fold increase in power handling over the SiP approach. From a time-to-market perspective, 3D SoC plots out a little bit longer than SiP because of the silicon processing that is required. For 3D SoC, the concept to product development cycle takes three to six months.
The bonds that tie
The bonding technique used in this process is the result of ten years of research at North Carolinas Research Triangle Institute. It is a covalent bonding technique with qualities of magnetic attraction. The different levels of the device are held together by the formation of covalent bonds. This bond is stronger than the silicon itself.
To date, none of the bonds formed by this process have delaminated. The integrity of the bond has been well established; it has been run through high temperature cycling, four-point bend tests and high temperature storage. In addition, injection moulding and die pull tests have proven that the process is reliable. The bonds will not sheer, bend or break off.
An innovative technology
3D SoC methodology is available now and the industry is interested in collaborating to develop tools and design software for these devices.