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Single wafer processing offers several advantages over the batch approach, especially in the field of wafer wet processing. SEZ Group vice president of corporate planning Heinz Oyrer reports.

Single wafer processing offers several advantages over the batch approach, especially in the field of wafer wet processing. SEZ Group vice president of corporate planning Heinz Oyrer reports.

For the semiconductor industry, like many other maturing industries, these are uncertain times. Driven by a consumer market of more sophisticated end-user products that are smaller, faster and cheaper, integrated device manufacturers (IDMs) are struggling to keep up with the latest technology and trends while maintaining a profitable business model.

While many factors affect the cost structure for chip production, the outlay associated with capital equipment remains key. Increasing emphasis is being placed on manufacturing models that offer flexibility and high productivity while minimising footprint and cost-of-ownership (CoO). This, we contend, will drive the industry towards the increasing use of single-wafer processing and away from the more traditional batch approach.

Out with the old...
Traditionally, the wet-processing market has been led by batch processing, in which multiple wafers are cleaned simultaneously in the same chamber typically via an immersion technique. This approach has proven effective for many previous technology nodes. It has offered acceptable performance with high throughput, and its capabilities and limitations are well understood. However, since the 130nm technology node, there have been increasing signs that the batch approach is reaching its limits. Newer, more demanding technologies - coupled with increasing emphasis on cost and risk reduction - have moved the spotlight away from batch technologies and onto single-wafer approaches.

There have also been growing efforts to "process match" technologies to streamline integration progress throughout the fab. Thus, from deposition to litho, from diffusion to cleans, the single-wafer concept is becoming the dominant philosophy [1]. Philosophy and practice do not always readily align, however. While the concept of single-wafer, particularly in cleans, is being welcomed intellectually, in practice its adoption has been slower.

The market for single-wafer depends, to a large extent, both on the customers technology node and its geographical location. Globally, the single-wafer approach is being adopted heavily in newly built fabs. In Asia in particular, there has been great investment in single-wafer wet-processing equipment. But in more mature markets, such as the United States and Europe, financial considerations have prevented implementation of single wafer even though fab managers recognise its advantages.

For companies still involved in technologies at the 90nm node or larger, the adoption of single-wafer wet-processing tools is much slower, simply because the trade-off between a new capital expenditure and its technical advantages is not favourable. But for advanced logic and dynamic random-access memory (DRAM) fabs working at the sub-90nm nodes, single-wafer is becoming the norm. The 65nm node appears to be the critical change-over point when single-wafers many advantages become too great to ignore.

In packaging, both batch and single-wafer machines are used today. But within three to five years, it is likely that the most advanced processes will use only single-wafer equipment (see Figure 1). We believe that within the same period, the vast majority of IC manufacturers will be predominantly using single-wafer processing. This change will eventually trickle down to the packaging houses a few years afterwards [2].

In the case of cutting-edge technologies, time-to-market is critical. This can be seen from the PC market with the constant drive towards faster and more functional logic chips. In most cases, the first to market was the dominant player and secured the majority share. Because of the markets cyclical nature, the ability to respond to market changes by controlling inventory has also become increasingly important. Better control of inventory could have a normalising effect on the market, aiding better capital planning by the industry and preventing the draconian measures that are usually taken as a result of market inequity. Lastly, overall manufacturing cost reduction is essential to maintain the long-term health of the industry and assure profitability throughout the supply chain.

Single-wafer processing offers many business advantages - faster time-to-market, better inventory control and lower overall manufacturing costs, to name a few. These benefits are starting to improve chipmakers ability to manage their supply chains and better deal with the "feast or famine" cycles that have long plagued the industry.

Nowadays, single-wafer processing is quite common in some critical modules - lithography, chemical vapour deposition, chemical-mechanical planarisation and etching are all single-wafer processes. However, many thermal processing steps, like silicon dioxide growth, diffusion and annealing are all done in batches of up to 200 wafers at a time in large tube furnaces. It is unlikely, at least in the short term, that these processes will change.

However, in the field of wet processing, the move towards single wafer processing has already begun. Surface preparation via wet processing is required at critical points throughout the integration flow. This preparation is typically in the form of cleaning, etching or stripping (figure 2). One subset of wet processing, more commonly known as wet cleaning, is performed to address three critical issues: reduction in defectivity, either as particles or ionic species, removal of films by an etching process, or the stripping of residues by chemical solvation (the process by which residues are made soluble).

Wet cleaning has typically been considered a non-value-added process - a necessary evil - but as technology requirements tighten with decreasing geometries and increasing material complexity, the benefits of wet cleans - improved device performance and die yield - are becoming more apparent. with the new
SEZs inception in 1986 introduced single-wafer wet processing technology, heralding a new concept in wafer surface preparation. The initial driver behind the single-wafer concept was process enhancement rather than cycle-time reduction. While the former is still critical to all IC technology and in particular logic devices, the latter has become the key industry driver, especially for DRAM manufacturing.

Single wafer tools were initially used in backside applications such as bulk film removal, backside metal decontamination, and silicon wafer thinning and surface modification [3]. However, in the last seven years, SEZ has developed more and more single wafer wet processing techniques for applications that have been traditionally implemented via batch.

Post-etch residue removal, for example, is now increasingly being carried out using single-wafer tools. This application will be the largest near-term growth area for single-wafer wet processors.

To assure its leadership in this field, SEZ is developing high-performance, high-throughput single-wafer wet-processing equipment that provides process performance superior to that of existing batch systems, with equivalent throughput (traditionally, batch systems biggest advantage over competitive tools) [4].

Key selling points of the new tools include decreased footprint and increasingly competitive CoO. Importantly, they also help chip makers boost yield levels. To build on these advantages, SEZ has programmes to develop new applications in low- and high-k material cleans, wafer bevel-edge cleans, metal silicide and salicides treatments, and speciality materials decontamination, to name but a few.

One of the key potential growth areas for single-wafer is front-end-of-line (FEOL) applications, which account for around 60% of the cleaning steps in a process flow, 38% of which take place prior to thermal steps. These typically involve the classical SC1 clean developed by Werner Kern (figure 3). Also, as many as 70% of all FEOL cleans involve the use of sulphuric-peroxide mixtures (SPM). These two application areas will be the focus of SEZs development efforts, and represent an enormous opportunity for the single-wafer approach.

For defectivity-critical cleans such as pre-diffusion and pre-gate cleans, the technical challenge is daunting. Presently, there appear to be few, if any, processes that will clean extremely small (<65nm) particles from extremely small (<40nm) features, such as delicate poly lines, without significant damage or excess material loss. A successful solution to this problem, particularly one based on a single-wafer approach, will revolutionise the industry and pose a serious threat to one of the last strongholds of batch-based cleaning technologies.

Finding the right approach to addressing this problem is almost as complex as the problem itself. There is considerable debate about the efficacy of megasonics technology for particle removal without inducing the customary damage. There is also great concern about how to effectively implement a suitable drying technology that will produce watermark-free surfaces without inducing damage or organic contamination.

Finally, the success of single-wafer wet processing has the potential to open up a whole new application space. To date, a large number of processes are being pursued using dry, plasma-based technologies such as photoresist and anti-reflective coating (ARC) removal. There is great concern about the ability of plasma technology to extend below the 65nm node because of via poisoning and structural damage. Hence, leading-edge IC manufacturers have expressed interest in evaluating all-wet approaches to resist, residue and ARC removal, creating an enormous opportunity for single-wafer wet processing.

The economics of change
According to Peter Gaboury, equipment programmes manager for STMicroelectronicss Central Front-end Manufacturing Methods Efficiency Group, "more productivity, better return on investment, optimising our installed capacity: these are challenges we face every day in the semiconductor industry - challenges that are becoming more and more difficult to achieve.

"The technology treadmill - the increasing technical complexity of our products - makes our job much more difficult; to this you can also add the need for speed - getting products faster to market - as a major factor increasing the difficulty.

"The conclusion is inescapable: as our industry matures, the ability to react quickly with the correct decision becomes the primary factor for success." [5]

Historically, productivity enhancement has been achieved through scaling, by reducing the chip size, increasing the wafer size and increasing production volume. Consequently, the key challenge of the supplier is to help IDM customers achieve these goals. Ways of doing this include offering cost-competitive solutions, working in close co-operation with customers to develop advanced processes and equipment, and providing rapid troubleshooting and cost-effective solutions for process problems.

Given the progress in reducing feature sizes, suppliers that want to compete effectively must be able to deliver solutions that address manufacturing requirements at 65nm device geometries and below. SEZs strategy centres on meeting these requirements by developing processes that offer greater productivity and technological advantages at the lowest CoO. To achieve this, the company has developed a two-pronged approach aimed at ensuring close relationships with global customers while capitalising on regional opportunities.

Firstly, SEZ intends to be at the forefront of technology development, focused not on being consistently too early to market, but on developing the best solution in a reasonable timeline. Secondly, the company will develop products and processes that will help customers reduce CoO. This means reducing manufacturing costs, improving process performance to diminish use of consumables, and using environmentally friendly materials to minimise the costs of handling and disposal.

Single-wafer cleaning, as well single-wafer technology in general, is one of the remaining key growth sectors for the semiconductor industry. SEZ is poised to set the standards here, based on its pioneering 20 years experience in this field, while managing the myriad cultural and social hurdles to ensure that single-wafer becomes the new manufacturing standard for 65nm and smaller devices.

Single-wafer processing equipment is gaining an ever growing market share


Figure 1. Wet processing market (US$M) - single wafer gaining popularity


Figure 2. Typical wet process steps on 90nm devices


Figure 3. FEOL - doubling addressable single-wafer wet processing market


[1] MICRO Magazine, April 2004 - "Batch Wet Process Still Dominates Wafer-Cleaning Market," Bijan Moslehi

[2] IEEE Spectrum Online: Feature Article, February 2005 - "Chip Makings Singular Future," Rajendra Singh and Randhir Thakur

[3] 4th International Conference on Advanced Thermal Processing of Semiconductors, September 1996 - "Backside film removal and its impact on semiconductor production," Hans Kruwinus

[4] European Semiconductor, June 2003 - "Single Wafer Renaissance," Heinz Oyrer

[5] FUTURE FAB International, Issue 11 - "Equipment Process Time Variability: Cycle Time Impacts," Peter Gaboury

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