News Article
New approach needed to overcome copper resistivity
Copper resistivity will remain a challenge for the semiconductor industry, but chip designers are likely to use hierarchical design workarounds to modify the metal for linewidths at the 45nm technology node, according to attendees at a recent industry workshop sponsored by Sematech and Novellus Systems.
Copper resistivity will remain a challenge for the semiconductor industry, but chip designers are likely to use hierarchical design workarounds to modify the metal for linewidths at the 45nm technology node, according to attendees at a recent industry workshop sponsored by Sematech and Novellus Systems.
The workshop focused on ways to extend the use of copper in advanced semiconductors in the face of increasing copper resistivity at linewidths below 90nm.
"Due to the fundamental laws of physics, copper resistivity is bound to increase and will result in several critical issues that need to be addressed," said Andreas Knorr, conference co-chair and manager of Sematechs advanced materials development programme.
"Various process refinements could alleviate perhaps 5% to 15% of the problem, provided that chip manufacturers are willing to accept added cost and design complexity."
Below 90nm linewidths, copper resistivity rises dramatically because of increased electron scattering on grain boundaries and interfaces. These resistivity increases can sharply diminish or wipe out the capacitance benefits of low-k dielectric materials, which have long been an industry focus.
"The increase in resistivity of an ultra-thin wire was of academic interest long before the first IC", said Ron Powell, conference co-chair and Novellus fellow. "But we have been so successful at scaling down CMOS devices and wiring that we now have to consider the practical impacts of these 'size effects' as well."
"Ironically, the switch from aluminium to copper wiring has accelerated the problem, since size effects show up in copper at closer-in technology nodes. Regardless of how the situation came about, it is likely to be addressed by a synergistic combination of materials, process and design changes," Powell added.
The workshop focused on ways to extend the use of copper in advanced semiconductors in the face of increasing copper resistivity at linewidths below 90nm.
"Due to the fundamental laws of physics, copper resistivity is bound to increase and will result in several critical issues that need to be addressed," said Andreas Knorr, conference co-chair and manager of Sematechs advanced materials development programme.
"Various process refinements could alleviate perhaps 5% to 15% of the problem, provided that chip manufacturers are willing to accept added cost and design complexity."
Below 90nm linewidths, copper resistivity rises dramatically because of increased electron scattering on grain boundaries and interfaces. These resistivity increases can sharply diminish or wipe out the capacitance benefits of low-k dielectric materials, which have long been an industry focus.
"The increase in resistivity of an ultra-thin wire was of academic interest long before the first IC", said Ron Powell, conference co-chair and Novellus fellow. "But we have been so successful at scaling down CMOS devices and wiring that we now have to consider the practical impacts of these 'size effects' as well."
"Ironically, the switch from aluminium to copper wiring has accelerated the problem, since size effects show up in copper at closer-in technology nodes. Regardless of how the situation came about, it is likely to be addressed by a synergistic combination of materials, process and design changes," Powell added.
