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From Lab To Fab

It is becoming increasingly important for metrology to analyse chips in more than two dimensions. Nick Dawes, Todd Henry and Doug Hahn of FEI Company report on a technology that brings the third dimension to bear.

Conventional top-down metrology is unable to provide the threedimensional perspective that is increasingly required to develop and monitor advanced semiconductor manufacturing processes. This problem will only grow more acute as device sizes continue to shrink and processes become more complex. Traditional cross sectional scanning electron microscopy (XSEM) can provide the required information but, due largely to capacity constraints, it is slow and costly since the wafers are sent out of line and are scrapped. The latest generation of DualBeam systems (CLM-3D, FEI Company) provides complete threedimensional characterisation in minutes and is fully compatible with wafer return. The following article discusses how CLM-3D provides timecritical process development, qualification and control data.


The value of three-dimensional data is well established. This is evidenced by the thousands of SEM cross sections made every week to support the needs of process, yield and integration engineers. Shortened technology life cycles and industry transitions, such as non-planar gates, high aspect ratio structures and new materials, are expected to further increase the need for threedimensional structural analysis.


Furthermore, the competitive nature of the semiconductor industry is driving companies to shorten development and yield ramp periods to maximise revenue for each technology node. As a result, engineers are being required to characterise and optimise processes in increasingly compressed time periods. These shorter learning cycles are driving fabs to transition some of the previous high volume, lower resolution labcentric analysis processes from the lab to the fab, This allows engineers to complete studies without leaving the clean room. As the more routine crosssectional work is being automated by tools like the CLM 3D, failure analysis groups can focus their highly-skilled resources on the more complex and ultra-high resolution needs of the fab, further extending the value proposition of in-line threedimensional analysis. This increasing need for rapid cross sectional information is not limited to process development; it also applies to in-line process control. Fabs are beginning to demand three-dimensional data to support process tool qualification and monitor complex structures that are buried or have re-entrant angles that cannot be monitored with conventional top-down metrology approaches. Although the lab-based XSEM does provide three-dimensional information, the excessive turn-around time and need to sacrifice wafers are even more costly in high-volume production than in process development.


In-fab DualBeam analysis provides results in minutes while also allowing the wafers to be returned to the line for further processing. FEIs CLM-3D, specifically designed for in-line metrology, combines a focused ion beam (FIB) for cross sectioning with an SEM for high resolution imaging. The measurement process is completely automated including navigation to the targeted site, cross sectioning, high resolution image collection, image analysis, CD measurement and data reporting.


DualBeam measurements are site specific and have no physical or electrical impact on neighbouring die, allowing the wafer to continue in the production process.


The value of inline cross sectional measurements is clear. In process development applications, users report a three-to-ten-times reduction in learning cycle times for process characterisation and process window optimisation. In process control applications, the benefits are equally compelling, with shortened time-to-results allowing faster recovery from yield excursions and significant reductions in the amount of inventory that is put at risk.


Applications
In-line three-dimensional imaging is being applied to a wide range of FEOL and BEOL layers to characterise and optimise processes in development and monitor key tools in production. The following section details some of the current layers that are routinely being imaged on the CLM tool.


Contacts/vias
At each new technology node, contact sizes get progressively smaller while aspect ratios increase. Development engineers require detailed contact size and profile information to characterise and optimise process conditions and integration sequences. Non-optimised contact formation processes can result in a variety of problems including (1) inadequate bottom diameter, which increases resistance and reduces operational speed; (2) insufficient depth, which creates open contacts; (3) over-etch that results in break through of the stop layer into the underlying polysilicon layer creating a variety of defects; and 4) in copper processes, too much barrel shape can lead to discontinuities in the barrier/seed layer, potentially allowing copper diffusion into surrounding structures and voids in the plated copper fill.


Figure 1 shows the result of an automated analysis of an isolated contact. The fill material visible in the image is tungsten that was deposited by the FIB as part of the analysis procedure to preserve the shape of the open contact during the milling operation. The system has the capability of simultaneously collecting a wide variety of measurements from different parts of the contact structures, including diameters and wall angles at various heights. This example includes an etchstop layer. The same type of analysis may be performed without the etch-stop to characterise the etch rate independently. The process can be set up to cut multiple slices to ensure capture of a full three-dimensional volumetric rendition of the geometry anywhere along a structure (including an isolated contact).


Shallow trench isolation (STI)
FEOL structures are receiving increasing attention at the <65nm advanced technology nodes. Shallow trench isolation is a technique that places trenches filled with dielectric material between active regions to enhance electrical isolation while still providing high device density. The shape of the trench, particularly the bottom corners and sidewall angle, are important to device performance. The dimensions of the active area control the speed of the device. The active area at the top of each space can be occluded by the nitride etch mask, making it difficult to characterise top down, especially in combination with the remaining nitride thickness. The depth of the trench is critical to ensure proper isolation.


Improper wall angle and corner profile can lead to silicon dislocations during thermal annealing, resulting in a breakdown of isolation between the source and drain. The CLM tool can obtain the critical dimensions, including active area, nitride thickness, and STI wall angle measurements, needed for process optimisation. In a fully automated analysis, the CLM steps across the wafer to pre-programmed sites and cross sections through the target structures to the desired point and then automatically collects the prescribed three-dimensional data.


Chemical mechanical planarisation
CMP processes were initially introduced to remove accumulated topography from the dielectric layers of multilevel interconnects. With the advent of dual damascene copper processes, CMP became an integral part of the interconnect definition process. The thickness of the copper lines and the dimensions of the dielectric separation are key determinants of electrical performance and therefore the speed and reliability of the device. A number of variables control CMP performance, including polishing time, pressure, slurry type and age, pad wear and pattern density. CMP processes require extensive monitoring to maintain performance within the process window. The effects of pattern density can be particularly difficult to overcome since they generally require in-circuit measurements that exceed the lateral resolution of global film thickness measurement techniques and the thickness resolution of top-down SEM.


Figure 3 compares cross sections of copper lines before and after CMP. Line width, space width, copper thickness and dielectric thickness are readily accessible for measurement.


Wafer mapping
Controlling process uniformity across the wafer is critical to maintaining yield. Maintaining uniformity has become more difficult with the move to 300mm wafers. Because of the time required for conventional cleave and polish cross sections, uniformity is typically monitored by comparing a single measurement in the centre with another near the edge. The low sampling density limits the sensitivity of the measurement and the lengthy delay in receiving results is not suitable for real time process control.


Figure 4 maps the active area CD for an STI etch process over the full wafer. The example shown uses 40 cross sections at user defined locations. The figure highlights the importance of sampling density by comparing the range of the 40 measurements (14%) to the difference that might have been reported (3%) using the more limited cleave and polish "centre and edge" approach. Full wafer mapping has the additional advantage of revealing spatial patterns that may indicate the source of non-uniformity.


Conclusion
The proliferation of new processes and materials, the move to 300mm wafers and the increasing three-dimensional complexity of device structures have combined to drive more sophisticated process development techniques and increase the value of three dimensional structural analysis for process control. In-line analysis provides high resolution three-dimensional characterisation in a fraction of the time required for conventional cross sectional SEM.


In process development, it accelerates the learning cycle, reducing time-to-market for new products and resulting ultimately in increased profitability and market share. Moreover, it is fully compatible with wafer return and suitable for inline use for high-volume production. The increased speed of analysis significantly reduces the amount of WIP at risk from a process excursion.


In the years to come, we expect that there will be a paradigm shift bringing an increasing number of what were traditionally lab-based analytical techniques into the fab.


This move from the lab to the fab will enable characterisation and rapid deployment of higher performance, more complex semiconductor devices.













Figure 1. Automated analysis of an automatically cross sectioned and imaged isolated contact. The analysis provides detailed measurements of contact diameter and sidewall angle at various heights


 










Figure 2. Shallow trench isolation. The automated analysis provides active area, nitride cap thickness, active area CD and sidewall angle


 










Figure 3. Copper interconnect before (left) and after (right) CMP. The analysis can provide precise measurements of the width and thickness of both the copper line and the dielectric.


 










Figure 4. Full wafer mapping for process uniformity. The map plots 40 measurements of the STI active area CD taken at various locations distributed over the full wafer surface. The increased sampling density reveals a 14% range, compared to the 3% that might have been detected by a conventional centre and edge analysis.






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