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News Article

Sematech develops pore-sealing for 45nm low-k

Engineers from US research consortium Sematech have developed an innovative poresealing technique that appears to prevent metal and precursor penetration into low-k dielectric materials, easing the introduction of low-k at the 45nm technology node.

Engineers from US research consortium Sematech have developed an innovative poresealing technique that appears to prevent metal and precursor penetration into low-k dielectric materials, easing the introduction of low-k at the 45nm technology node. The potential solution calls for sealing the sponge-like pores in low-k materials through a chemical vapour deposition (CVD) sequence that achieves a very high degree of conformity with minimal impact on keffective.

"Sematech has long been committed to identifying manufacturable low-k materials and processes for our members to use in advanced manufacturing," said Sitaram Arkalgud, the consortium's interconnect director. "Here we have the basis of a true solution that will solve the industry's pressing problem of getting these materials ready for the 45nm node."

Low-k materials are porous substances that are much less dense than silicon dioxide, the starting material for semiconductors, or chips. Lowk is critical to advanced semiconductor manufacturing because it allows metal lines to be packed closer together on a chip with less risk of electrical signal leakage, which can create interference problems within the chip. Throughout the late-1990s and early-2000s, the semiconductor industry drove relentlessly toward developing materials with progressively decreasing k-values, but process induced damage to these materials is becoming increasingly problematic as the industry approaches the 45nm node.

Sematech's work in this area supports the industry goal of obtaining an effective k-value of 2.5 for the 45nm node, which is slated to enter production in 2010. Pore sealing is critical to advanced low-k development because conducting metals such as copper (as well as precursor chemicals used in conjunction with them) tend to penetrate low-k materials during CVD or atomic layer deposition (ALD). Such penetration, which occurs in standard damascene processing, causes increased current leakage, heightened capacitance, and degradation in the reliability of chip structures. However, Sematech's technique alters the damascene process by applying a commercially available material through CVD after etching. The material penetrates the vertical walls of the etched dielectric to seal the pores, but does not leave an "overburden" of pore sealant along the side walls.

According to a Sematech spokesman, "the new approach provided both pore sealing and protection from dielectric damage," with no evidence of copper penetration into the lowk, and significantly less carbon depletion.

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