Stress relief

The effects of mechanical stress of chemical mechanical planarisation (CMP) have continued to limit the successful adoption of low-k and ultra low-k dielectric films used in copper metallisation schemes needed for advanced technology nodes. To some degree, this has resulted in the industry continuing to push out full adoption of low-k solutions and, in particular, ultra low-k.

ACM Researchs stress-free polishing - the Ultra SFP stress-free polishing system - was first developed as a process solution that avoided the mechanical stress associated with using CMP for the final polishing of copper interconnect films.

The initial ACM process is a "drop-in addition" to conventional back-end-of-line (BEOL) operations using CMP; its chemical-based polishing renders copper flat and stops at the tantalum/tantalum nitride (Ta/TaN) barrier layer.

It also results in planarisation free of the common erosion problems associated with conventional CMP. The Ta/TaN layer is removed evenly via a subsequent plasma etch. Ultra SFP tools are being evaluated successfully at leading IC wafer fabs.

Problems with using CMP for planarisation down to and through the barrier film include: 

• The flatness of planarisation becomes more difficult (ie, topographic features are unevenly removed through well documented dishing and erosion);
• The mechanical pressure used with CMP is detrimental to underlying fragile low-k dielectric films (recent work at ACM quantified the poor mechanical strength of ultra low-k films [1]); and
• The removal of the barrier layer exposes the underlying low-k dielectric to surface damage and contamination.

The initial ACM Research Ultra SFP process is a significant improvement to CMP for final polishing of copper and removal of the underlying barrier layer.

Further development and patent-pending work at ACM Research has refined its electro-chemical copper-polishing process so that - with copper low-k processes using tantalum (Ta) and other pure metal barrier layers - the barrier layer oxidises during electro-chemical polishing.

This converts the barrier layer into a dielectric that caps the low-k dielectric film and eliminates the need to remove the barrier layer. One of the main advantages of this approach is the sealing of the dielectric layer from any type of contamination (eg moisture, chemical gases, solvents, particles, etc).

The standard damascene copper low-k process includes depositing or spinning on the low-k film, etching trenches, contacts and vias, depositing a barrier layer, depositing a copper seed layer, and copper plating (see Table 1).

The initial use of tantalum/tantalum nitride (Ta/TaN) for the barrier layer is giving way to using just tantalum (Ta); TaN was originally adopted because of concerns over the potential of copper diffusing into the low-k dielectric, but this issue has mitigated.

Currently, Ta is increasingly the metal of choice because thinner layers can be used and Ta has a much lower resistance in contacts and vias compared to TaN. With Ta films, researchers have reported that there is no diffusion of copper through the Ta barrier into silicon until 650°C [2].

In addition, a lot of electromigration data is available based on the interface between Ta and copper.

Table 1 compares the steps needed - for conventional CMP, Ultra SFP with Ta/TaN barriers and Ultra SPF with Ta barriers - after copper plating to planarise the interconnect level prior beginning the next level:

• The conventional CMP process sequence uses low pressure and finer polishing pads and slurries to remove the final 2000Å of copper and the barrier layer; as we have already noted, this process suffers from increasing difficulties as linewidths decrease and, in particular, when a low-k dielectric is used.
• Electro-chemical planarisation with Ta/TaN barriers is a two-step process where the final copper is removed via Ultra SPF and the Ta/TaN barrier layer is removed via a subsequent plasma etch step.
• When the barrier film is pure Ta, the electro-chemical polishing process removes the final copper overburden and then anodises the tantalum barrier film to tantalum oxide (Figure 2), a dielectric that does not have to be removed and is compatible with the interconnect structure.

Table 1 summarises the advantages and disadvantages of each of these process approaches.

SIMS profiles taken before and after the electrochemical oxidation of a typical 20Å Ta barrier film show that the oxidation of the Ta film is complete and to a depth equal to or greater than the initially deposited film (Figure 2). Work is on going to study the phases of the resulting TaO and to evaluate the added benefits of the subsequent anneals used in copper processing. (Annealing of TaO is commonly used in fabricating tantalum capacitors to eliminate leakage current.)

While TaO has a relatively high dielectric constant (ie, a k value around five times high than silicon dioxide), the resulting, relatively thin TaO layer does not line the walls of the copper trenches, contacts and vias so the cumulative effect of the TaOs dielectric constant does not significantly increase the effective k value of lowk films between adjacent copper trenches within the same metal layer. Further, there is no TaO on the top surface of copper trenches so there is less impact on the effective k value between adjacent metal levels.

The big advantage when using Ultra-SFP with a Ta barrier layer is that once the barrier layer is deposited, the low-k film is isolated from physical and chemical contact with anything that happens in the process. Many of the problems associated with the integration of copper and low-k today involve specific problems with the low-k film and the impact on the k value: surface damage, delamination, exposure to moisture and chemicals, etc.

Because this new process leaves the asdeposited Ta layer in place and only converts it chemically to a TaO cap, all these problems are reduced or eliminated. In addition, initial evaluations show that the resulting TaO cap over the low-k dielectric eliminates any potential for decreasing time dependent dielectric break down (TDBD) that could result from damage or contamination of the low-k film surface post CMP. Finally, this durable cap on the low-k films also make post-planarisation cleaning more straightforward.

While actual cost of ownership advantages resulting from using electro-chemical planarisation with Ta barrier films will vary from fab to fab, it is likely to achieve a more cost effective process sequence. Savings will result from eliminating the need for costly pads and fine-grit, temperature-sensitive slurries in the final CMP polishing and TaN removal steps and from circumventing the need to reduce CMP down pressure that results in less throughput in CMP.

Obviously, the biggest gain will come from increases in yield because the electro-chemical polishing with Ta greatly lessens or eliminates all the classic yield limiting problems that have been linked to using conventional CMP with copper low-k interconnect.

Ultra SPF with Ta barrier films is a solid route to enabling the fabrication of copper low-k interconnect schemes with consist yields.

Conclusion
When used with copper low-k processing that includes pure Ta barrier layers, the ACM Ultra SFP process has some key advantages over other CMP-based alternatives:

• Final copper polishing and chemical oxidation of the Ta barrier layer can be done with one tool that is a "drop in" addition to conventional CMP fabs;
• Oxidisation of the Ta barrier layer means that it is not removed, resulting in a continuous cap on the underlying low-k or ultra low-k films;
• The underlying low-k dielectric is protected from physical damage and sealed from exposure to chemicals and moisture; and
• The TaO cap helps to eliminate particle and other defects to the low-k film, which is an extremely difficult and unsolved problem in post CMP processing.

References:
1. D Wang, "A Crucial Message from the Quantification of Copper Ultra Low-k Mechanical Strength," pending publication.
2. T Laurila, K Zeng, JK Kivilahti, J Molarius, I Suni, "Chemical stability of Ta diffusion barrier between Cu and Si," Thin Solid Films 373 (2000), pp 64-67