+44 (0)24 7671 8970
More publications     •     Advertise with us     •     Contact us
*/
News Article

Nano-Imprint Lithography Standards

The International Technology Roadmap for Semiconductors (ITRS) has adopted nanoimprint lithography (NIL) as a contending Next Generation Lithography (NGL) for technology nodes ²32nm. Standards will be required to support the commercialization. Helge Luesebrink from EV Group and Carlos Lee from SEMI report.

Advances in academic research and early stage developments in commercialization of micro/nano patterned devices via print and imprint technologies (Fig. 1) have caught the industrys attention. These developments provide opportunities for process simplification, potential for cost efficient device manufacturing and enable novel devices and applications that bridge the world of semiconductor manufacturing with alternative micro-, and nanofabrication technologies.

The installed base for NIL processing equipment from various suppliers promotes a wide variety of processes, template / stamp and substrate formats. Consequently, efforts are required to enable a clear communication within the industry on processes (hot embossing, SFIL, etc.) and their respective template/stamp and substrate requirements. It is estimated that there were over 160 systems installed for R&D in nanoprint and nanoimprint technologies by the end of 2004 with an anticipated growth of ~15%. NIL related equipment sales are estimated to reach $35 million in 2007.

History of Nanoimprint
The technology of imprint has been known for over 2000 years as a reliable, high throughput pattern replication method for various products such as coins, graphics and data storage media. Through its potential for accuracy, resolution and throughput, the application areas for imprint have extended to semiconductor manufacturing for low cost definition of nanostructures. Milestones in this development were achieved by J. Haisma et al.[i] from Philips and S. Chou from the Princeton University [ii]. Although both groups used imprint techniques for definition of nanostructures on silicon wafers, their approaches differed in one important point: the imprint resist. Chous approach used the thermoplastic resin PMMA that was heated above its glass transition temperature up to its liquid state. The replication process was started and then the system was cooled down again. Haismas approach was to press the SiO2 mould into a low viscous monomer. After the imprint procedure through the backside of the mould, it was cured under UV-light. Since then research groups have become interested in the technology and activities began around the world either using Chous or Haismas approach.

Although in the beginning the use of thermoplastic resin for imprint was favoured by the majority of the imprint community, the UVcuring approach became more and more accepted in recent years. Impediments to further development of the hot embossing technologies include time consuming thermal cycles that reduce accuracy through different thermal expansions of mould and substrate, as well as extremely high imprint pressures that make precision overlay in the sub-100 nm regime difficult.





In UV Nanoimprint (Fig. 3), developed by AMO and RWTH [iii] in 1997, low viscous UV-curable imprint resists are used in step and repeat mode for full wafer patterning in reduced ambient pressure after spin coating of the resist. Concurrently Step&Flash Lithography (SFIL)[iv] was developed at University of Texas where a dispense technique is used to apply the imprint resist in drops prior to the imprint cycle carried out under normal ambient pressure [v][vi]. In both approaches low imprint pressure (< 300 mbar) is applied to enable ultra fine alignment by observing marks through the transparent template. Improvements have been recorded in alignment accuracy, throughput and yield

Standardization
A large range of feature sizes and surface structures can be replicated in a single step by NIL providing process simplification and low cost material alternatives to conventional lithography processes. To make NIL a reality in semiconductor manufacturing, developments are required in template fabrication, resist definition, process control and metrology. The SEMI Standards Micropatterning Technical Committee established a new task force to tackle those questions during SEMICON Europa in April 2005. Headed by EV Groups Helge Luesebrink, Director Business Unit Advanced Lithography, the NIL standardization task force inaugural meeting during SEMICON West in July 2005 attracted significant attention from blank mask suppliers (Schott Lithotec, Asahi Glass), mask houses (DNP, Photronics, Toppan), next generation lithography and metrology equipment suppliers (ASML, EVG, FEI Company, KLA Tencor, Leica Microsystems, Molecular Imprints), as well as semiconductor manufacturers and suppliers (Agilent Technologies, Dow Corning, HP).

As a result of the meeting, Molecular Imprints Doug Resnick, Vice President Template Technology, and Asahi Glass Mamoru Takahashi, New Business Development Division, volunteered to be the co-chairs of the international task force in the US and in Japan respectively.

The efforts of this task force focus on UVNanoimprint lithography for step and repeat methods due to its compatibility to conventional lithography techniques in semiconductor manufacturing. Starting with subsurface defect issues in standard 6025 mask blanks, the activities will emphasise compatibility and commercially available infrastructure from materials and processes via equipment compatibility to technical and administrative issues such as template handling and ordering guidelines.





The task force sets out to collect, evaluate and define the infrastructure for NIL template design and specification to accelerate commercialization and help to make NIL a reality in manufacturing. The activity is set to run in its initial phase as a 24-month program. The next meeting is scheduled to take place in conjunction with the SEMI Europe Standards Autumn Event 26-28 October 2005 in Leuven (www.semi.org/eustan dards). If you wish to participate, please contact H. Luesebrink on email: H.Luesebrink@EVGro up.com or C. Lee at clee@semi.org

References
1 J. Haisma et al., "Template-assisted nanolithography: A process for reliable pattern replication" JVST B14 (6), 4124, (1996)
1 S. Y. Chou et al., « Nanoimprint Lithography » JVST B 14(6), 4129, (1996)
1 "Fabrication of Nanostructures using an UV-based imprint technique"M. Bender, M. Otto, B. Hadam, B. Vratzov. B. Spangenberg, H. Kurz, Microelectronic Engineering, Vol. 53, pp. 233-236, 2000.
1 SFIL Trademark by Molecular Imprints, USA
1 M. Colburn et al.,"Step and Flash Imprint Lithography: An alternative approach to high resolution patterning" Proc. SPIE Vol. 3676, 379 (1999)
1 M. Colburn et al. "Step and Flash Imprint Lithography for sub-100 nm patterning" Proc. SPIE Vol. 3997, 453 (2000)

 

×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: