Wafer Thinning Products
Starting around 1980 with the introduction of dual-in-line packages (DIPs), wafer thinning has become an industry requirement. Package thickness has been driven down from about 4 mm to about 0.5 mm for applications like smart card modules and miniature ball grid arrays (BGAs). Data shows that the industry has decreased chip thickness by about 5% each year since 1980. The major drivers for wafer thinning are the need to reduce the thermal resistance for better heat dissipation in fast devices, to increase the device reliability in flip-chip packages, and to enable manufacturers to design and build stacked devices. The bestknown application is the use of thinned devices in smart cards and flexible media. Since smart cards have about the same thickness as standard credit cards (750 microns), the respective microchips have to be about 200 microns in thickness. In general, development efforts have focused on thinner wafers and even “super thin” dies to be used in a new generation of contactless smart cards2. Developed in Japan, the overall thickness of these smart cards is only 250 microns which will require extremely thin dies with a thickness of only 100 microns. For comparison: a sheet of paper is about 75 to 80 microns thick.
Other emerging applications for thinned devices include micro-electro-mechanical systems (MEMS) (which have a predicted annual growth rate of 10 % over the next ten years) and the use of tags for Radio Frequency Identification (RFID) which will be applied to consumer products throughout the logistic chain. (Fig. 1) The typical thickness of a 0.7 x 0.7 mm RFID-chip is less than 150 μm.
Further applications for wafer thinning include the manufacture of thinned silicon circuitry for use in electro-optic devices, thin multi-chip modules and “substrate-less” multi-chip modules. Typical multi-chip applications are combinations of memories (flash, SRAM and fast cycle RAM) into a single package3 for use in cellular phones.
It is clear that the use of wafer thinning technology is highly important for many applications and our use of this technology will only increase in the future.
Methods of Wafer Thinning
The main methods utilized for wafer thing are: 1. mechanical grinding and polishing, 2. chemical mechanical polishing (CMP), 3. wet chemical etching and 4. plasma etching using atmospheric downstream plasma (ADP). Often a combination of the different techniques is applied to obtain the best results. The thinning process can be divided into several steps. First, the wafer is mounted to a mechanical grinder unit and an abrasive wheel with typically 35 - 500 grit diamond abrasive which removes a bulk portion of the silicon. The silicon removal rates are around 5 μm/sec in this step. Then a fine abrasive wheel removes most of the structural grinding damage by a more gentle grinding with fine abrasives of 2000 - 3000 grit. With a thinning rate of less than 1 μm/sec., the fine grind removes about 20 microns and most of the damage caused by the coarse grinding.
The effect of the mechanical treatment on the silicon surface is best illustrated by atomic force microscope (AFM) photos of silicon wafers after grinding4. Fig. 2 shows the silicon surface after coarse grinding, indicating considerable damage. The surface still exhibits residual damage after this and some of the coarse grind damage remains even after the fine grind (Fig. 3). This method presents problems for the edge of the wafer. This critical area becomes sharpened during the grinding process and therefore is much more vulnerable to chipping or indenting when it comes into contact with a hard surface.
The CMP process, typically applied for planarization on the wafer front side, uses buffered slurries containing suspended abrasives and stabilizing additives in combination with special polishing pads. This method provides very flat surfaces with low thickness variation. However, as the removal rates are only few microns per minute, the CMP process is not suitable for large volume wafer thinning processes.
Plasma etching for wafer thinning is a relatively new method. The dry etching process uses an argon-CF4 plasma at atmospheric pressure in the downstream mode (ADP). Even though the thinning rates (about 20 μm/min) and the etch uniformity are acceptable, the plasma process itself causes some defects near the surface.
Wet chemical etching has emerged as the best choice for the wafer thinning process. It does not induce defects like those found from plasma etching while alternate options involving grinding experience problems as the wafer gets thinner: the mechanical stability is reduced, and combined with the impact of the remaining damage from the grinding process, the wafers break easily. Final wet chemical etching offers a gentle and effective solution to this problem. The damage zones are removed by a variety of silicon etchants, typically applied on a SEZ single-wafer spin-processor5, leaving either a reflective or a textured surface, according to the user’s requirements. The chemical spin-etch process appears to be the only way to obtain extremely thin wafers, as it is impossible to produce wafers thinner than 120 microns by grinding alone. The design of advanced spin-etching tools allows different etchants to be applied subsequently to the wafer surface. As the different processes are performed at different height levels within the tool, recovery and reuse of the etchants is possible, as shown in Fig. 4.
Chemical Silicon Etchants
Wet etching of silicon basically requires two chemical species: an oxidizer to convert the silicon into silicon oxide and a source of fluoride to dissolve the silicon oxide into soluble fluorosilicic acid. The most commonly used oxidizer is nitric acid while hydrofluoric acid is generally used as source of fluoride. Mixtures of hydrofluoric acid (HF) and nitric acid (HNO3) at various ratios etch silicon rapidly, however, the uniformity of the etch over a larger area (a wafer surface) is not satisfactory. Addition of acetic acid (CH3COOH) to the composition works as a modifier leading to better results with respect to surface roughness and uniformity. The spin-etch technology in contrast to etching in a wet bench also requires the viscosity of the etchant to be adjusted. This is generally accomplished by the addition of sulphuric acid (H2SO4) and ophosphoric acid (H3PO4) to the composition, both of which are chemicals with high viscosities. Data collected from a survey of multiple semiconductor manufacturers showed several different etchant compositions used for silicon etching. A graphical overview is given in Fig. 5. From this portfolio 4 etchant compositions of major importance have been selected for further evaluation and optimization.
The etchants are:
Bulk Silicon Etchant
Silicon Polish Etchant I
Silicon Polish Etchant II
Silicon Texture Etchant.
Etch rate tests run according to DIN 50 453-16 confirm that the concentrations of HF and HNO3 in the mixtures are the main factors influencing the etch rates. Looking at the concentration distribution of the different acids in the respective etchants (Fig. 5), it becomes obvious that the
chemical composition of etchants targeted to
create a given surface roughness differs from
those used to remove bulk silicon and leave a
smooth and shiny surface. It is observed that the
major difference between the texture etchants
and the polish etchants is the concentration of
sulphuric acid and the water-content of the
composition. In texture etchants the sulphuric
acid concentration is high while the water
content is between 6 and 10 %, whereas in bulk
silicon etchants and polishing silicon etchants the
water content is around 25-30 %. The amount of
water seems to contribute to the transition from
texturing the silicon surface to polishing it.
Following this, some considerations are made
regarding how to utilize the water content of the
system for improved etchant performance.
More detailed studies on the relations between
etchant composition and etch performance lead
to the conclusion that the compositions of the
etchants are critical to variations in etch rate and
surface roughness. This results in a proposal for
tighter control limits for the manufacturing
process to achieve a minimum of variation. As an
example, the influence of introducing tightened
specification limits to critical composition
components is shown for the HF assay of Bulk
Silicon Etchant (Fig. 6 and 7). Tighter specification
limits increase the process capability significantly
and the conclusion that this also affects the
variation in etch performance is obvious.
To evaluate the influence of tool parameter settings on the uniformity and etch rate of Bulk Silicon Etchant, tests were run on a spin-processor tool. The etch non-uniformity and, to a lesser extent, the etch rate, can be modified by adjusting the appropriate spin etching tool parameters. The etch rate and etch rate non-uniformity of the Bulk Silicon Etchant as a function of the parameter settings of a SEZ Model 203 Spin-Processor, configured for 200 mm wafers, are presented as an example. The SEZ Spin-Processor is a singlewafer wet surface preparation tool that utilizes a rotating process chuck. After a wafer is placed on a chuck, it rotates at a controllable rate (chuck speed). The etchant is dispensed onto the rotating wafer through a movable nozzle suspended above the rotating wafer. The etchant temperature and flow rate are controlled. The etchant dispensing nozzle can move back and forth in a plane that is perpendicular to the plane containing the rotating wafer. The length of this movement is called the dispense profile.
Surface and contour plots of the silicon etch non-uniformity of the Bulk Silicon Etchant as a function of chuck speed and temperature when the settings of the other tool parameters (flow rate and dispense profile) are held at their middle settings are presented in Fig. 8a and Fig 8b respectively. The silicon etch non-uniformity is primarily determined by the chuck rotational speed. The silicon etch non-uniformity, for example, decreases from approximately +6 (center fast) to -4 (center slow) percent as the chuck speed increases from 400 to 800 RPM while the temperature is held constant at 25 ºC. A chuck speed of 750 RPM and temperature of 25 ºC yields an absolutely uniform (U = 0) etch. The etchant temperature has a large effect on the silicon etch uniformity when the chuck speed is high. The silicon etch non-uniformity decreases from +2 (center fast) to -7 (center slow) percent as the temperature increases from 22 to 28 ºC. while the chuck speed is held constant at 800 RPM. The etch non-uniformity, however, remains near +6 (center fast) percent as the temperature is increased from 22 to 28 ºC. while the chuck speed is held constant at 400 RPM.
Surface and contour plots of the silicon etch rate of the Bulk Silicon Etchant as a function of chuck speed and temperature when the settings of the other tool parameters (flow rate and dispense profile) are held at their middle settings are presented in Fig. 9a and Fig. 9b respectively. The silicon etch rate is primarily determined by the chuck rotational speed. The silicon etch rate, for example, increases from approximately 27 to 38 _m/minute as the chuck increases from 400 to 800 RPM while the temperature is held constant at 25ºC. The etchant temperature has less of an effect than the chuck speed on the silicon etch rate. The silicon etch rate, for example, only increases from 31 to 33 _m/minute as the temperature increases from 22 to 28ºC. while the chuck speed is held constant at 600 RPM. Line testing will continue using the wafer thinning etchants with improved compositions to verify the preliminary results on a broader scale.
Wafer thinning technologies are vital for many applications and the necessity to thin wafers will increase for years to come. Although there are various methods used to achieve thinner wafers, a closer look reveals that wet chemical etching is the preferred choice. This article the authors sought to provide details of methods used and present data collected from Honeywell’s research and development efforts around the use of wet chemical etching for wafer thinning.
References
1. S. Savastiouk, O. Siniaguine and E. Korczynski (2000), 3-D stacked wafer-level packaging. Advanced Packaging, March 2000, pp 28-34
2. G. Wagner (2000-2001) Improving Wafer Thinning with Spin-Processing. (ver. dat. Aug. 6, 2001, 15:30 MEZ) http://www.link2semi.com/articles/tut060111.jsp
3. P. Kallender (2001) Fujitsu stacks three memories in multichip package. (ver. dat. Aug. 7, 2001, 10:45 MEZ) http://www.eetimes.com/story/OEG20010703S0033
4. P. Halahan, P. Marcoux, F. Kretz, T. Schraub (2002), Backgrinding Technologies for Thin-Wafer Production. Chip-Scale Electronics, Jan.-Febr. 2002 (ver.dat. Dec. 06, 2002, 15:10 MEZ)
5. Ch. McHatton and C. Gumbert, Eliminating backgrind defects with wet chemical etching. Solid State Technology, Nov. 1998
6. DIN 50453-1 Bestimmung der Ätzraten von Ätzmischungen (Oct. 1990), available through Beuth Verlag GmbH, Burggrafenstrasse 6, D-10772 Berlin
