Reducing assembly cost for RFID

The application possibilities of RFID are endless. Technical analysis shows that broad-based applications of RFID will develop in two distinct phases. Phase 1, which we are in right now, is showing only marginal advances because RFID is superficially tacked onto existing business processes. Phase 2 will offer a truly revolutionary change after radical process re-engineering and new RFIDcentred business models will emerge. This phase will unlock the full potential of RFID and turn it into a new base technology. In additional, analysts say that industry executives are only focusing on the price of RFID tags and when they will come down. Instead, the industry should dedicate more creative resources to advancing manufacturing technologies.

Nevertheless, price is the significant benchmark for RFID tags to be accepted in broadbased markets. Today, there is talk of the "nickel tag", a fully functional passive RFID transponder for just a nickel (5 US cents) per unit, which will be available by 2008. Back in 2003, the average price point of RFID tags was ten times this value. But now there is evidence of a new wave of technology enablers that will drive the production cost of RFID tags down. The focus here is the cost of chip assembly, which can be implemented with various methods as will be described below.

Developing RFID Chip Assembly
The method of assembling a chip onto a substrate has been developed and optimized for decades and is known as conventional die bonding technology. Based on this know-how, equipment vendors derived advanced die bonding machines which can do high-speed flip chip assembly. Due to the proposed huge volume demand of RFID tags, a couple of alternative approaches (for example, Fluidic Self Assembly [1] and Vibratory Assembly [7]), referred to as "visionary approaches" in this context, seem to offer a solution for the challenge (fig. 1).

The big advantages of conventional and advanced die bonding equipment are both mature technology with the benefit of low investment risk and high-yield operation. To give a better idea: For the assembly of high-end flip chip devices like DSPs and ASICs, an assembly yield of >99.95% is a standard target. For low-end flip chip devices like RFID tags, a yield of 98% is standard, an optimization to 99% yield is realistic if all process and material parameters are well controlled, and 99.5% should be a reachable in the mid-term timeframe.

The following simple calculation helps explain the cost pareto of yield loss: A complete chip assembly line including adhesive application, flip chip attach, curing, testing and slitting is currently available at a market price of <1,000,000 US$. With 7400 hours' productive time, a line throughput of 10000 UPH, and 5 years' depreciation, the costs of chip assembly are 0.27 US cents per tag. Assume further 15 US cents for the costs of an RFID tag and consider a yield loss of 2%. Then the cost of the yield loss is 0.3 US cents, which exceeds the depreciation costs of the equipment. This calculation example should help to illustrate the high value of mature high-yield assembly equipment.

Direct and Indirect Chip Assembly
In the manufacturing of RFID tags, there is a basic distinction between direct chip assembly and indirect chip assembly (fig. 2).

In direct assembly, the chip's bumps are positioned and placed directly onto the antenna connections by means of flip chip technology. The key advantage is a lower packaging cost, because this requires fewer process steps and consumes

less material. However, despite the large antenna pitch, high throughput rates necessitate negligible indexing timing. Thus - with a conventional flip chip bonder approach - the technology is not without its challenges, which will be more manageable the bigger the bonding area of the antenna web. However, the trade-off with a bigger bonding area is longer travel time for chip transport. A well-balanced dimensioning of the bonding area will result in a successful machine concept (fig. 3).

As an alternative, various manufacturers employ indirect RFID chip assembly. Indirect assembly, as a first process step, introduces a flip chip interposer. In a subsequent step, at very high throughput and low cost of ownership, the interposer is mounted on the antenna, which can be done by crimping. Indirect assembly is advantageous especially for manufacturers who have no previous experience with bare-chip processing and do not want to invest in gathering the necessary know-how.

At the same time, investment costs for the follow-up assembly step are significantly lower. The trade-off here is higher packaging costs. Also, crimp connection quality is still a very controversial matter. Therefore, alternative methods such as soldering or adhesive interconnection methods are being used. Or the connection is facilitated after the interposer is glued onto cardboard and the antenna is applied in a second step via the printing of conductive ink over both cardboard and interposer.

Flip Chip and Process Flow
An additional choice has to be made for the type of interconnection method. Fig. 4 shows the various options that are generally available.

In terms of RFID chip assembly, the most promising technologies are NCA (non-conductive adhesive) and ACA (anisotropic conductive adhesive) [4]. Since the pre-applied epoxy also functions as an underfiller, the interconnection technology is very cost-effective, especially in paste form (NCP, ACP).

The epoxy can be applied by screen printing or dispensing, whereby dispensing saves further costs because the process consumes less material.Bearing in mind that NCP is less expensive than ACP, the ideal interconnection technology seems to be dispensed NCP.

The advantages of NCP are listed below:

• Easy, fast, low-cost processing
• High-quality interconnection
• No additional underfill
• Few process steps
• Low epoxy cost
• Heat compliant with low-cost substrate materials
• Usable for reel-to-reel applications

The feasibility of high-volume NCP production on flex substrate has also been demonstrated in smartcard production, where the high reliability requirements of the flip-chip packages has been proven.

In addition, the non-collapse soldering process is used for RFID chip assembly. For example, the GBS process (gold bump soldering) benefits from the low bumping costs of the gold bump and the high quality of the intermetallic interconnection due to soldering.

To complete the picture: Collapse processes are not feasible because of higher bumping costs, thicker package profiles, and the need for an extra underfill step, unless pre-applied underfill is used. The ICA process too is inferior because it requires the extra underfilling step.

Ultrasonic (US) and Thermosonic (TS) require mechanically stable support from the substrate, which is not easy to achieve with low-cost materials like PET at thicknesses of 50µ and below.

Chip Assembly Process Flow
As a final consideration, the various options of process flow for chip assembly must be understood. The classic flow, which has been used for NCP production, starts with epoxy application (screen printing or dispensing), followed by the pick-flip-place (die attach). Curing takes place in a two-stage process: parallel lamination of a couple of dies in a heated press station (pre-curing) [4] and final curing in an inline oven.

Experience has shown that the number of process steps in the classic flow can be reduced by going with either the place and laminate flow, which does not need an inline oven for final curing, or the place and cure flow, which eliminates the lamination in the heated press.

The place and laminate flow is very widely used in RFID inlay production for NCP and ACP packages, but has its trade-offs in line throughput.

Fig. 6 shows the achievable throughput of a heated press depending on the number of dies per index (to be laminated in parallel) and the curing dwell time, assuming 2 seconds for the nonproductive time during index, open and close of the heated press.

Assuming 7500-10000 UPH for a flip chip bonder, depending on the antenna size, the line UPH can be essentially bottlenecked by the heated press, especially for production of big UHF inlays.

This is one major reason why place and cure assembly solutions, which are standard for soldering processes, are in the focus for future investments [2,3,4].

The 5 cent tag
Coming back to the question of whether a sales price of 5 US cents will be realistic in the next few years, a widely used view of the RFID label's cost budget is as follows:

IC manufacturing costs
(thinned, bumped, diced wafer) < 2 cents
Antenna manufacture < 1 cent
Inlay assembly (including chip attach) < 1 cent
Label conversion < 1 cent
Total < 5 cents

Listening to the semiconductor manufacturers, RFID IC manufacturing for less than 2 cents will be realistic for high volumes [2,5,7]. Also antenna manufacture and label conversion technologies are developing toward a cost target of < 1 cent each. It is beyond the scope of this article to give a detailed picture of the cost map for all combinations of technological approaches for inlay assembly. Instead the cost budget for a particular turnkey assembly solution is presented, which will definitely be a benchmark for all winning technologies in the future.

The depreciation costs are based on 5 years and 7400 productive hours per year; operating costs are based on 30 $/h including environmental costs, where each operator can serve 5 lines. Yield loss is based on 98% yield and 15 cents inlay costs. Based on a 2-year-outlook, the author proposes that equipment suppliers will be able to double the UPH of the assembly lines at constant equipment costs, and the yield should be increased to 99.5% while inlay costs are dropping below 5 cents. This results in the following midterm cost budget benchmark for RFID inlay assembly:

Depreciation costs for
chip assembly: < 0.11 cents
Depreciation costs for dispensing: < 0.01 cents
Depreciation costs for test & slit: < 0.02 cents
Operating costs: < 0.03 cents
Adhesive costs: < 0.05 cents
Yield loss: < 0.03 cents
Total inlay assembly < 0.25 cents

To manufacture RFID tags at very low cost, it is essential to understand the different technology approaches for RFID inlay production. The introduction of new visionary technologies will essentially depend on the yield costs which come along with these technologies. In this context, a benchmark based on mature turnkey production technology has been presented, which calculates inlay assembly costs of <0.68 cents at the current time, where chip assembly costs are below 0.22 cents. In addition there is a two-year outlook with <0.25 cents for total inlay assembly and <0.11 cents for chip assembly.